R5F5631BCDLC#U0 datasheet, PDF

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R5F5631BCDLC#U0: DescriptionIC MCU 32BIT 1MB FLASH 177TFLGA; Categorysemiconductor The embedded processor and controller; File Size2MB，210 Pages; ManufacturerRenesas Electronics Corporation; Websitehttps://www.renesas.com/; Environmental Compliance

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R5F5631BCDLC#U0 Overview

IC MCU 32BIT 1MB FLASH 177TFLGA

R5F5631BCDLC#U0 Parametric

Parameter Name	Attribute value
core processor	RX
core size	32-bit
speed	100MHz
Connectivity	CANbus，EBI/EMI，I²C，LINbus，SCI，SPI，USB
Peripheral	DMA，LVD，POR，PWM，WDT
Number of I/Os	133
Program storage capacity	1MB（1M x 8）
Program memory type	flash memory
EEPROM capacity	32K x 8
RAM capacity	128K x 8
Voltage - Power Supply (Vcc/Vdd)	2.7 V ~ 3.6 V
data converter	A/D 8x10b，21x12b，D/A 2x10b
Oscillator type	internal
Operating temperature	-40°C ~ 85°C（TA）
Package/casing	177-TFLGA
Supplier device packaging	177-TFLGA（8x8）

User Manual

【硬件手册】RX63N Group, RX631 Group User's Manual: Hardware Rev.1.80

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Features

RX63N Group, RX631 Group

Renesas MCUs

100-MHz 32-bit RX MCU, on-chip FPU, 165 DMIPS, up to 2-MB flash

memory, various communications interfaces including Ethernet MAC,

full-speed USB 2.0 host/function/OTG interface, CAN, 10- & 12-bit A/D

converters, RTC

R01DS0098EJ0180

Rev.1.80

May 13, 2014

Features

RX63N Group products incorporate an Ethernet controller while

RX631 Group products do not.

■

32-bit RX CPU core



Max. operating frequency: 100 MHz

Capable of 165 DMIPS in operation at 100 MHz

Single precision 32-bit IEEE-754 floating point

Two types of multiply-and-accumulation unit (between memories and

between registers)

32-bit multiplier (fastest instruction execution takes one CPU clock cycle)

Divider (fastest instruction execution takes two CPU clock cycles)

Fast interrupt

CISC Harvard architecture with 5-stage pipeline

Variable-length instructions: Ultra-compact code

Supports the memory protection unit (MPU)

JTAG and FINE (two-line) debugging interfaces

PLQP0176KB-A

PLQP0144KA-A

PLQP0100KB-A

PLQP0064KB-A

PLQP0048KB-A

24 × 24 mm, 0.5-mm pitch

20 × 20 mm, 0.5-mm pitch

14 × 14 mm, 0.5-mm pitch

10 × 10 mm, 0.5-mm pitch

7 × 7 mm, 0.5-mm pitch

PTLG0177KA-A 8 × 8 mm, 0.5-mm pitch

PTLG0145KA-A 7 × 7 mm, 0.5-mm pitch

PTLG0100JA-A 7 × 7 mm, 0.65-mm pitch

PTLG0064JA-A 6 × 6 mm, 0.65-mm pitch



PLBG0176GA-A 13 × 13mm, 0.8-mm pitch

■

Various communications interfaces

■

Low-power design and architecture



Operation from a single 2.7- to 3.6-V supply



Low power consumption: A product that supports all peripheral functions

draws only 500

μA/MHz.



RTC is capable of operation from a dedicated power supply (min. operating

voltage: 2.3 V).



Four low-power modes



Supports ROM-less versions and versions with up to 2 Mbytes of ROM

(ROMless/256 Kbytes/384 Kbytes/512 Kbytes: RX631 Group only)



100-MHz operation, 10-ns read cycle (no wait states)



768-Kbyte to 2-Mbyte capacities



User code is programmable by on-board or off-board programming



ROM-less or 32 Kbytes of ROM (reprogrammable up to 100,000 times)



Programming/erasing as background operations (BGOs)



64 Kbytes/128 Kbytes/192 Kbytes/256 Kbytes of SRAM



For instructions and operands



Can provide backup on deep software standby



DMAC: Four channels

DTC

EXDMAC: Two channels

Dedicated DMAC for the Ethernet controller: Single channel

■

On-chip main flash memory, no wait states



Ethernet MAC (1) (not in RX631 Group products)



Host/function or OTG controller (1) and function controller (1) with full-

speed USB 2.0 transfer



CAN (compliant with ISO11898-1), incorporating 32 mailboxes (up to 3

modules)



SCI with multiple functionalities (up to 13)



Choose from among asynchronous mode, clock-synchronous mode, smart-

card interface mode, simplified SPI, simplified I2C, and extended serial

mode.

C bus interface for transfer at up to 1 Mbps (up to 4)



RSPI for high-speed transfer (up to 3)



Parallel data capture unit (PDC) (1) (available for 512 Kbytes/384 Kbytes/

256 Kbytes flash memory with 177-pin, 176-pin, 145-pin, and 144-pin)



Buses for high-speed data transfer (max. operating frequency of 50 MHz)

8 CS areas (8 × 16 Mbytes)

Multiplexed bus or separate bus are selectable per area.

8-, 16-, or 32-bit bus space is selectable per area

Independent SDRAM area (128 Mbytes)

■

External address space

■

On-chip data flash memory

■

On-chip SRAM, no wait states

■

Up to 20 extended-function timers

■

DMA



16-bit MTU2: input capture, output compare, PWM waveform output,

phase-counting mode (6 channels)



16-bit TPU: input capture, output compare, phase-counting mode (12

channels)



8-bit TMR (4 channels)



16-bit compare-match timers (4 channels)



Up to 21 × 12-bit channels, and incorporating 1 sample-and-hold circuit

Up to 8 × 10-bit channels, and incorporating 1 sample-and-hold circuit



Addition of results of A/D conversion (in the 12-bit converter)



Self diagnosis (for the 10-bit converter)

■

A/D converter for 1-MHz Operation

■

Reset and supply management



Power-on reset (POR)



Low voltage detection (LVD) with voltage settings



External crystal oscillator or internal PLL for operation at 4 to 16 MHz



Internal 125-kHz LOCO and 50-MHz HOCO



125-kHz clocks for the IWDT



Adjustment functions (30 seconds, leap year, and error)



Time capture function

(for capturing times in response to event-signal input on external pins)



125-kHz LOCO clock operation

■

Clock functions

■

10-bit D/A converter: 2 channels

■

Temperature sensor for measuring temperature within

the chip

■DEU



AES encryption and decryption functions



128/192/256-bit key length



ECB/CBC mode

■

Real-time clock

■

Independent watchdog timer

■

Useful functions for IEC60730 compliance

■

important registers against overwriting.

■

Up to 134 pins for general I/O ports

■

Unique ID



5-V tolerance, open drain, input pull-up, switchable driving ability



16-byte ID code is provided for each chip (only for the G version)



D version: -40 to +85°C



G version: -40 to +105°C



Oscillation-stoppage detection, frequency measurement, CRC, IWDT, self-

diagnostic function for the A/D converter, etc.

■

Operating temp. range

R01DS0098EJ0180 Rev.1.80

May 13, 2014

Page 1 of 208

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