EEWORLDEEWORLDEEWORLD

Part Number

Search

570ABC000173DGR

Description
ANY, I2C PROGRAMMABLE XO
CategoryPassive components   
File Size562KB,36 Pages
ManufacturerSilicon Laboratories Inc
Download Datasheet Parametric View All

570ABC000173DGR Online Shopping

Suppliers Part Number Price MOQ In stock  
570ABC000173DGR - - View Buy Now

570ABC000173DGR Overview

ANY, I2C PROGRAMMABLE XO

570ABC000173DGR Parametric

Parameter NameAttribute value
typeXO (Standard)
FunctionEnable/Disable (Reprogrammable)
outputLVPECL
Voltage - Power2.97 V ~ 3.63 V
frequency stability±20ppm
Absolute pulling range (APR)-
Operating temperature-40°C ~ 85°C
Current - Power (maximum)130mA
grade-
Installation typesurface mount
Package/casing8-SMD, no leads
size/dimensions0.276" long x 0.197" wide (7.00mm x 5.00mm)
Si 5 7 0 / S i 5 7 1
10 MH
Z
Features
TO
1.4 G H
Z
I
2
C P
ROGRAMMABLE
XO/VCXO
Any programmable output
frequencies from 10 to 945 MHz and
select frequencies to 1.4 GHz
I
2
C serial interface
3rd generation DSPLL
®
with superior
jitter performance
3x better frequency stability than
SAW-based oscillators
Internal fixed crystal frequency
ensures high reliability and low
aging
Available LVPECL, CMOS,
LVDS, and CML outputs
Industry-standard 5x7 mm
package
Pb-free/RoHS-compliant
1.8, 2.5, or 3.3 V supply
Si5602
Applications
Ordering Information:
SONET/SDH
xDSL
10 GbE LAN/WAN
ATE
High performance
instrumentation
Low-jitter clock generation
Optical modules
Clock and data recovery
See page 31.
Pin Assignments:
See page 30.
(Top View)
SDA
7
NC
1
6
V
DD
Description
The Si570 XO/Si571 VCXO utilizes Silicon Laboratories’ advanced DSPLL
®
circuitry to provide a low-jitter clock at any frequency. The Si570/Si571 are user-
programmable to any output frequency from 10 to 945 MHz and select frequencies
to 1400 MHz with <1 ppb resolution. The device is programmed via an I
2
C serial
interface. Unlike traditional XO/VCXOs where a different crystal is required for
each output frequency, the Si57x uses one fixed-frequency crystal and a DSPLL
clock synthesis IC to provide any-frequency operation. This IC-based approach
allows the crystal resonator to provide exceptional frequency stability and
reliability. In addition, DSPLL clock synthesis provides superior supply noise
rejection, simplifying the task of generating low-jitter clocks in noisy environments
typically found in communication systems.
OE
2
5
CLK–
GND
3
8
SCL
4
CLK+
Functional Block Diagram
V
DD
CLK-
CLK+
Si570
SDA
7
OE
Fixed
Frequency
XO
10-1400 MHz
DSPLL Clock
Synthesis
V
C
1
6
V
DD
SDA
SCL
OE
2
5
CLK–
Si571 only
ADC
GND
3
8
SCL
4
CLK+
GND
V
C
Si571
Si570/Si571
Rev. 1.6 6/18
Copyright © 2018 by Silicon Laboratories
Charging IC status output judgment
Which method is better to judge the status output of the charging IC so that the status output of the charging IC is stable and has a certain level signal?...
QWE4562009 Power technology
Protel99SE shortcut key sharing
VF: Display the whole PCB diagram L: PCB layer attributes TT: Add teardrop TD: Design rule check and then ALT+R to complete the design rule check TP: Whole PCB parameter setting DS: PCB update schemat...
single MCU
Are people who don't like analog microcontrollers but like FPGA destined to have a tragic ending?
[color=rgb(0,0,0)][color=rgb(68,68,68)][backcolor=rgb(255,255,255)] I am very conflicted about graduating soon. I have always hated C analog electronics and single-chip microcomputers. I would vomit w...
checksix Talking about work
atmel studio implements jlink's swd
[table=98%] [tr][td]How to use JLink's swd function to debug in atmel studio software? I just started using asf and was not familiar with everything. I could only run around randomly. Right-click on t...
star_66666 Microchip MCU
Introducing two Vishay ultra-small SMD quartz crystal oscillators
[i=s]This post was last edited by jameswangsynnex on 2015-3-3 20:03[/i]Introducing two Vishay ultra-small SMD quartz crystal oscillators In order to make your electronic devices smaller and lighter, V...
jameswangsynnex Mobile and portable
Help, experts please come in
1. Brief description The data in the program are defined as follows: LNAME DB 'IBM-PC test' , '$' ADDRESS DB 15DUP(0) ENTRY DB 3 CODE-LIST DB 11,7,8,3,2 1. Assume that the offset of LNAME relative to ...
lczzn2008 Embedded System

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 740  2172  2343  755  415  15  44  48  16  9 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号