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Dual, 16-Bit, 1000 MSPS,
TxDAC+ Digital-to-Analog Converter
AD9125
FEATURES
Flexible CMOS interface allows dual-word, word, or byte load
Single-carrier W-CDMA ACLR = 80 dBc at 122.88 MHz IF
Analog output: adjustable 8.7 mA to 31.7 mA, R
L
= 25 Ω to 50 Ω
Novel 2×/4×/8× interpolator/complex modulator allows
carrier placement anywhere in the DAC bandwidth
Gain and phase adjustment for sideband suppression
Multichip synchronization interface
High performance, low noise PLL clock multiplier
Digital inverse sinc filter
Low power: 900 mW at 500 MSPS, full operating conditions
72-lead, exposed paddle LFCSP
GENERAL DESCRIPTION
The AD9125 is a dual, 16-bit, high dynamic range TxDAC+®
digital-to-analog converter (DAC) that provides a sample rate of
1000 MSPS, permitting a multicarrier generation up to the Nyquist
frequency. It includes features optimized for direct conversion
transmit applications, including complex digital modulation,
and gain and offset compensation. The DAC outputs are optimized
to interface seamlessly with analog quadrature modulators, such
as the ADL537x F-MOD series from Analog Devices, Inc. A 4-wire
serial port interface allows programming/readback of many inter-
nal parameters. Full-scale output current can be programmed
over a range of 8.7 mA to 31.7 mA. The AD9125 comes in a
72-lead LFCSP.
APPLICATIONS
Wireless infrastructure
W-CDMA, CDMA2000, TD-SCDMA, WiMAX, GSM, LTE
Digital high or low IF synthesis
Transmit diversity
Wideband communications: LMDS/MMDS, point-to-point
Cable modem termination systems
PRODUCT HIGHLIGHTS
1.
Ultralow noise and intermodulation distortion (IMD)
enable high quality synthesis of wideband signals from
baseband to high intermediate frequencies.
A proprietary DAC output switching technique enhances
dynamic performance.
The current outputs are easily configured for various
single-ended or differential circuit topologies.
The flexible CMOS digital interface allows the standard
32-wire bus to be reduced to a 16-wire bus.
2.
3.
4.
TYPICAL SIGNAL CHAIN
COMPLEX BASEBAND
COMPLEX IF
RF
DC
f
IF
LO – f
IF
2
2/4
I DAC
ANTIALIASING
FILTER
AQM
PA
DIGITAL
BASEBAND
PROCESSOR
2
SIN
COS
2/4
Q DAC
LO
09016-001
NOTES
1. AQM = ANALOG QUADRATURE MODULATOR.
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2010 Analog Devices, Inc. All rights reserved.
AD9125
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Typical Signal Chain......................................................................... 1
Revision History ............................................................................... 2
Functional Block Diagram .............................................................. 3
Specifications..................................................................................... 4
DC Specifications ......................................................................... 4
Digital Specifications ................................................................... 5
Latency and Power-Up Timing Specifications ......................... 5
AC Specifications.......................................................................... 6
Absolute Maximum Ratings............................................................ 7
Thermal Resistance ...................................................................... 7
ESD Caution .................................................................................. 7
Pin Configuration and Function Descriptions ............................. 8
Typical Performance Characteristics ........................................... 10
Terminology .................................................................................... 16
Theory of Operation ...................................................................... 17
Serial Port Operation ................................................................. 17
Data Format ................................................................................ 17
Serial Port Pin Descriptions ...................................................... 17
Serial Port Options ..................................................................... 18
Device Configuration Register Map ............................................ 19
Device Configuration Register Descriptions .......................... 21
CMOS Input Data Ports ................................................................ 29
Dual-Word Mode ....................................................................... 29
Word Mode ................................................................................. 29
Byte Mode .................................................................................... 29
Interface Timing ......................................................................... 30
FIFO Operation .......................................................................... 30
Digital Datapath.............................................................................. 32
Premodulation ............................................................................ 32
Interpolation Filters ................................................................... 32
NCO Modulation ....................................................................... 35
Datapath Configuration ............................................................ 35
Determining Interpolation Filter Modes ................................ 36
Datapath Configuration Example ............................................ 37
Data Rates vs. Interpolation Modes ......................................... 38
Coarse Modulation Mixing Sequences.................................... 38
Quadrature Phase Correction................................................... 39
DC Offset Correction ................................................................ 39
Inverse Sinc Filter ....................................................................... 39
DAC Input Clock Configurations ................................................ 40
DAC Input Clock Configurations ............................................ 40
Analog Outputs............................................................................... 42
Transmit DAC Operation.......................................................... 42
Auxiliary DAC Operation ......................................................... 43
Baseband Filter Implementation .............................................. 44
Driving the ADL5375-15 .......................................................... 44
Reducing LO Leakage and Unwanted Sidebands .................. 44
Device Power Dissipation.............................................................. 45
Temperature Sensor ................................................................... 46
Multichip Synchronization............................................................ 47
Synchronization with Clock Multiplication ............................... 47
Synchronization with Direct Clocking .................................... 49
Data Rate Mode Synchronization ............................................ 49
FIFO Rate Mode Synchronization ........................................... 50
Additional Synchronization Features ...................................... 51
Interrupt Request Operation ........................................................ 52
Interrupt Service Routine .......................................................... 52
Interface Timing Validation .......................................................... 53
SED Operation............................................................................ 53
SED Example .............................................................................. 53
Example Start-Up Routine ........................................................ 54
Outline Dimensions ....................................................................... 55
Ordering Guide .......................................................................... 55
REVISION HISTORY
6/10—Revision 0: Initial Version
Rev. 0 | Page 2 of
56
AD9125
FUNCTIONAL BLOCK DIAGRAM
16
1.2G
DAC 1 AUX
16-BIT
IOUT1P
IOUT1N
DATA
RECEIVER
16
FIFO
f
DATA
/2
PRE
MOD
HB1
NCO
AND
MOD
HB2
HB3
10
I OFFSET
Q OFFSET
16
16
1.2G
DAC 1 AUX
16-BIT
D[31:0]
INV
SINC
DACCLK
DCI
FRAME
IOUT2P
IOUT2N
PHASE
CORRECTION
INVSINC_CLK
GAIN 1
HB1_CLK
HB2_CLK
HB3_CLK
INTP
FACTOR
MODE
GAIN 2
10
10
REF
AND
BIAS
REFIO
FSADJ
INTERNAL CLOCK TIMING AND CONTROL LOGIC
DAC CLK_SEL
PLL CONTROL
PROGRAMMING
REGISTERS
SERIAL
INPUT/OUTPUT
PORT
POWER-ON
RESET
MULTICHIP
SYNCHRONIZATION
SYNC
DACCLK
0
1
PLL_LOCK
CLOCK
MULTIPLIER
(2× TO 16×)
CLK
RCVR
CLK
RCVR
DACCLKP
DACCLKN
REFCLKP
REFCLKN
SDIO
IRQ
RESET
SDO
SCLK
CS
Figure 2. AD9125 Functional Block Diagram
Rev. 0 | Page 3 of
56
09016-002
AD9125
SPECIFICATIONS
DC SPECIFICATIONS
T
MIN
to T
MAX
, AVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, I
OUTFS
= 20 mA, maximum sample rate, unless otherwise noted.
Table 1.
Parameter
RESOLUTION
ACCURACY
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL)
MAIN DAC OUTPUTS
Offset Error
Gain Error (with Internal Reference)
Full-Scale Output Current
1
Output Compliance Range
Output Resistance
Gain DAC Monotonicity
Settling Time to Within ±0.5 LSB
MAIN DAC TEMPERATURE DRIFT
Offset
Gain
Reference Voltage
REFERENCE
Internal Reference Voltage
Output Resistance
ANALOG SUPPLY VOLTAGES
AVDD33
CVDD18
DIGITAL SUPPLY VOLTAGES
DVDD18
IOVDD
POWER CONSUMPTION
2× Mode, f
DAC
= 491.52 MSPS, IF = 10 MHz, PLL Off
2× Mode, f
DAC
= 491.52 MSPS, IF = 10 MHz, PLL On
8× Mode, f
DAC
= 800 MSPS, IF = 10 MHz, PLL Off
AVDD33
CVDD18
DVDD18
Power-Down Mode
Power Supply Rejection Ratio, AVDD33
OPERATING RANGE
1
Min
Typ
16
±2.1
±3.7
Max
Unit
Bits
LSB
LSB
−0.001
−3.6
8.66
−1.0
0
±2
19.6
10
Guaranteed
20
0.04
100
30
1.2
5
+0.001
+3.6
31.66
+1.0
% FSR
% FSR
mA
V
MΩ
ns
ppm/°C
ppm/°C
ppm/°C
V
kΩ
3.13
1.71
1.71
1.71
3.3
1.8
1.8
1.8/3.3
834
913
1114
55
78
440
1.5
3.47
1.89
1.89
3.47
V
V
V
V
mW
mW
mW
mA
mA
mA
mW
% FSR/V
°C
−0.3
−40
+25
1227
58
85
490
2.7
+0.3
+85
Based on a 10 kΩ external resistor.
Rev. 0 | Page 4 of
56
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