74VHCT574AFT datasheet, PDF - EEWORLD Datasheet

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74VHCT574AFT: DescriptionIC FF D-TYPE SNGL 8BIT 20TSSOP; Categorylogic logic; File Size177KB，9 Pages; ManufacturerToshiba Semiconductor; Websitehttp://toshiba-semicon-storage.com/; Environmental Compliance

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74VHCT574AFT Overview

IC FF D-TYPE SNGL 8BIT 20TSSOP

74VHCT574AFT Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Toshiba Semiconductor
Parts packaging code	TSSOP
package instruction	TSSOP,
Contacts	20
Reach Compliance Code	unknown
Factory Lead Time	12 weeks
series	AHCT/VHCT/VT
JESD-30 code	R-PDSO-G20
length	6.5 mm
Logic integrated circuit type	BUS DRIVER
Number of digits	8
Number of functions	1
Number of ports	2
Number of terminals	20
Maximum operating temperature	125 °C
Minimum operating temperature	-40 °C
Output characteristics	3-STATE
Output polarity	TRUE
Package body material	PLASTIC/EPOXY
encapsulated code	TSSOP
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
propagation delay (tpd)	13 ns
Filter level	AEC-Q100
Maximum seat height	1.2 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	AUTOMOTIVE
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	4.4 mm
Base Number Matches	1

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74VHCT574AFT

CMOS Digital Integrated Circuits Silicon Monolithic

74VHCT574AFT

1. Functional Description

•

Octal D-Type Flip Flop with 3-State Outputs

2. General

The 74VHCT574AFT is an advanced high speed CMOS OCTAL FLIP-FLOP with 3-STATE OUTPUT fabricated

with silicon gate C

MOS technology.

It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS

low power dissipation.

This 8-bit D-type flip-flop is controlled by a clock input (CK) and an output enable input (OE).

When the OE input is high, the eight outputs are in a high impedance state.

The input voltage is compatible with TTL output voltage.

This device may be used as a level converter for interfacing 3.3 V to 5 V system.

Input protection and output circuit ensure that 0 to 5.5 V can be applied to the input and output

input/output voltages such as battery back up, hot board insertion, etc.

Note: Output in off-state

(Note)

pins

without regard to the supply voltage. These structure prevents device destruction due to mismatched supply and

3. Features

(1)

(2)

(3)

(4)

(5)

(6)

(7)

(8)

AEC-Q100 (Rev. H) (Note 1)

Wide operating temperature range: T

opr

= -40 to 125



High speed: f

MAX

= 140MHz (typ.) at V

= 5.0 V

Low power dissipation: I

= 4.0

µA

(max) at T

= 25

Compatible with TTL inputs: V

= 0.8V (max)

= 2.0V (min)

Power-down protection is provided on all inputs and outputs.

Balanced propagation delays: t

PLH

≈

PHL

Low noise: V

OLP

= 1.5 V (max)

(9) Pin and function compatible with the 74 series (74ACT/HCT/AHCT etc.) 574 type.

Note 1: This device is compliant with the reliability requirements of AEC-Q100. For details, contact your Toshiba sales

representative.

Start of commercial production

2013-04

2016-08-04

Rev.3.0

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