1-to-8 Differential to Universal Output
Clock Divider/Fanout Buffer
General Description
The IDT8T79S818I-08 is a high performance, 1-to-8, differential input
to universal output clock divider and fanout buffer. The device is
designed for frequency-division and signal fanout of high-frequency
clock signals in applications requiring four different output
frequencies generated simultaneously. Each bank of two outputs has
a selectable divider value of ÷1 through ÷6 and ÷8. The
IDT8T79S818I-08 is optimized for 3.3V and 2.5V supply voltages and
a temperature range of -40°C to 85°C. The device is packaged in a
space-saving 32 lead VFQFN package.
IDT8T79S818I-08
DATASHEET
Features
•
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•
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Four banks of two low skew outputs
Selectable bank output divider values: ÷1 through ÷6 and ÷8
One differential PCLK, nPCLK input
PCLK, nPCLK input pair can accept the following differential input
levels: LVPECL, LVDS levels
Maximum input frequency: 1.5GHz
LVCMOS control inputs
QXx ÷1 edge aligned to QXx ÷n edge
Individual output divider control via serial interface
Individual output enable/disable control via serial interface
Individual output type control, LVDS or LVPECL, via serial
interface
2.375V to 3.465V supply voltage operation
-40°C to 85°C ambient operating temperature
Lead-free (RoHS 6) packaging
Pin Assignment
nQC0
nQC1
nQB0
nQB1
QBO
QC0
QC1
QB1
Block Diagram
VCC
PCLK
nPCLK
16
15
V
CC
V
EE
QD0
nQD0
QD1
nQD1
V
CC
PWR_SEL
Pulldown
Pullup/Pulldown
24
23
22
21
20
19
18
17
Dividers
RST
VEE
VEE
7
QA0
nQA0
QA1
nQA1
V
CC
V
EE
nQA1
QA1
nQA0
QA0
V
CC
SDATA
25
26
IDT8T79S818I-08
27
28
29
30
31
32
1
2
3
4
5
6
7
8
14
QB0
nQB0
QB1
nQB1
32 lead VFQFN
5mm x 5mm x 0.925mm
Pad size 3.15mm x 3.15mm
NL package
Top View
13
12
11
10
9
QC0
nQC0
PWR_SEL
Pulldown
QC1
nQC1
VEE
MISO
SCLK
nRST
PCLK
nPCLK
V
CC
QD0
nQD0
VCC
OE
LE
nRST
OE
LE
SCLK
SDATA
Pullup
Pulldown
Pulldown
Pulldown
Pulldown
QD1
nQD1
D ivid e r S e le ct,
O u tp u t T yp e a n d
O u tp u t E n a b le
lo g ic
12
10
MISO
VEE VEE VEE VEE
IDT8T79S818A-08NLGI REVISION A JULY 11, 2013
1
©2013 Integrated Device Technology, Inc.
IDT8T79S818I-08 Data Sheet
1-TO-8 DIFFERENTIAL TO UNIVERSAL OUTPUT, CLOCK DIVIDER/FANOUT BUFFER
Pin Description and Characteristic Tables
Table 1. Pin Descriptions
Number
1
2
Name
SCLK
MISO
Input
Output
Type
Pulldown
Description
Serial Control Port Mode Data Input. LVCMOS/LVTTL interface levels.
Serial Control Port Mode Data Output. LVCMOS/LVTTL interface levels.
Frequency Divider Reset. When the nRST is released (rising edge), the divided
clock outputs are activated and will transition to a high state simultaneously.
See also Timing Diagram. LVCMOS/LVTTL interface levels (“Figure
1. Timing
Diagram”).
Non-inverting differential clock input.
Inverting differential clock input. V
CC
/ 2 by default when left floating.
Default output disable. LVCMOS/LVTTL interface levels. See
“Table 3B. OE
Truth Table”.
Power supply voltage pin.
Pulldown
Pulldown
Output
Output
Power
Output
Output
Output
Output
Output
Output
Input
Pulldown
Serial Control Port Mode Load Enable. Latches data when the pin gets a high
level. Outputs are disabled when LE is low. LVCMOS/LVTTL interface levels.
Power supply selection. See
“Table 3A. PWR_SEL Truth Table”.
Differential output pair Bank D, output 1. LVPECL or LVDS interface levels.
Differential output pair Bank D, output 0. LVPECL or LVDS interface levels.
Negative power supply pins.
Differential output pair Bank C, output 1. LVPECL or LVDS interface levels.
Differential output pair Bank C, output 0. LVPECL or LVDS interface levels.
Differential output pair Bank B, output 1. LVPECL or LVDS interface levels.
Differential output pair Bank B, output 0. LVPECL or LVDS interface levels.
Differential output pair Bank A, output 1. LVPECL or LVDS interface levels.
Differential output pair Bank A, output 0. LVPECL or LVDS interface levels.
Serial Control Port Mode Data Input. LVCMOS/LVTTL interface levels.
3
nRST
Input
Pullup
4
5
6
7, 10, 16,
25, 31
8
9
11, 12
13, 14
15, 26
17, 18
19, 20
21, 22
23, 24
27, 28
29, 30
32
PCLK
nPCLK
OE
V
CC
LE
PWR_SEL
nQD1, QD1
nQD0, QD0
V
EE
nQC1, QC1
nQC0, QC0
nQB1, QB1
nQB0, QB0
nQA1, QA1
nQA0, QA0
SDATA
Input
Input
Input
Power
Input
Pulldown
Pullup /
Pulldown
Pulldown
NOTE:
Pullup and Pulldown
refer to internal input resistors. See
“Table 2. Pin Characteristics”
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLUP
R
PULLDOWN
R
OUT
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Output Impedance
MISO
V
CC
= 3.3V
V
CC
= 2.5V
Test Conditions
Minimum
Typical
2
51
51
125
145
Maximum
Units
pF
k
k
IDT8T79S818A-08NLGI REVISION B JULY 11, 2013
2
©2013 Integrated Device Technology, Inc.
IDT8T79S818I-08 Data Sheet
1-TO-8 DIFFERENTIAL TO UNIVERSAL OUTPUT, CLOCK DIVIDER/FANOUT BUFFER
Function Tables
Table 3A. PWR_SEL Truth Table
PWR_SEL
L (Connect to V
EE
)
H (Connect to V
CC
)
Function
2.5V power supply
3.3V power supply
Table 3B. OE Truth Table
OE
L (default)
H
Function
All outputs disabled (Low/High static mode), regardless of individual OE registers set by Serial Interface.
Outputs enabled according to individual OE registers set by Serial Interface (see
“Table 3E. Configuration
Table”).
IDT8T79S818A-08NLGI REVISION B JULY 11, 2013
3
©2013 Integrated Device Technology, Inc.
IDT8T79S818I-08 Data Sheet
1-TO-8 DIFFERENTIAL TO UNIVERSAL OUTPUT, CLOCK DIVIDER/FANOUT BUFFER
Output Type Control and Start-up Status
Two output types are available: LVDS and LVPECL. The part features
four modes of output type controls, see Table 3C.
Disabled outputs are in static Low/High LVDS mode. At start-up, all
outputs are disabled (i.e. in static Low/High LVDS mode) until the part
has been configured. A global hardware Output Enable (OE pin #6)
enables or disables all outputs at once. The global hardware OE has
priority over serial interface configuration.
Table 3C. Output Type Control
Control Bits
D2
LOW
HIGH
HIGH
LOW
D1
LOW
HIGH
LOW
HIGH
Output Configuration
8 LVDS outputs
8 LVPECL outputs
2 LVDS (QAx) +
6 LVPECL (QBx, QCx, QDx) outputs
2 LVPECL (QAx) +
6 LVDS (QBx, QCx, QDx) outputs
Frequency Divider
Each output bank can be individually set to output an integer division
of the input frequency. Factors of 1, 2, 3, 4, 5, 6 and 8 are available
and are programmed by a serial interface.
The nRST pin resets the dividers. When the nRST pin is released, all
output dividers are activated and will transition to a high state
simultaneously.
QXn (/ 1)
QXn (/ 2)
QXn (/ 3)
QXn (/ 4)
QXn (/ 5)
QXn (/ 6)
QXn (/ 8)
Figure 1. Timing Diagram
IDT8T79S818A-08NLGI REVISION B JULY 11, 2013
4
©2013 Integrated Device Technology, Inc.
IDT8T79S818I-08 Data Sheet
1-TO-8 DIFFERENTIAL TO UNIVERSAL OUTPUT, CLOCK DIVIDER/FANOUT BUFFER
Serial Interface
Configuration of the IDT8T79S818I-08 is achieved by writing 22
configuration bits over serial interface. All 22 bits have to be written in
sequence.
After writing the 22 configuration bits, the LE pin must remain at high
level for outputs to toggle.
t
HI
t
LO
t
SH
SCLK
SDATA
t
SL
D22
t
S
D21
t
H
D3
D2
D1
LE
t
HE
t
DELAY
MISO
D22
D21
D3
D2
D1
Figure 2. Serial Interface Timing Diagram for Write and Read Access
Table 3D. Timing AC Characteristics
Symbol
t
S
t
H
t
HE
t
HI
t
LO
t
SL
t
SH
t
DELAY
Parameter
Data to Clock Setup Time
Data to Clock Hold Time
Clock to LE Hold Time
Clock High Duration
Clock Low Duration
LE to Clock Setup Time
LE to SCLK Setup Time
Clock to MISO Delay Time
Test Conditions
Minimum
10
10
10
25
25
10
10
10
Typical
Maximum
Units
ns
ns
ns
ns
ns
ns
ns
ns
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
IDT8T79S818A-08NLGI REVISION B JULY 11, 2013
5
©2013 Integrated Device Technology, Inc.
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