TC74HC4051,4052AP/AF/AFT,4053AP/AF/AFN/AFT
TOSHIBA CMOS Digital Integrated Circuit
Silicon Monolithic
TC74HC4051AP,TC74HC4051AF,TC74HC4051AFT
TC74HC4052AP,TC74HC4052AF,TC74HC4052AFT
TC74HC4053AP,TC74HC4053AF,TC74HC4053AFN,TC74HC4053AFT
TC74HC4051AP/AF/AFT
8-Channel Analog Multiplexer/Demultiplexer
TC74HC4052AP/AF/AFT
Dual 4-Channel Analog
Multiplexer/Demultiplexer
TC74HC4053AP/AF/AFN/AFT
Triple 2-Channel Analog
Multiplexer/Demultiplexer
The TC74HC4051A/4052A/4053A are high speed CMOS
ANALOG MULTIPLEXER/DEMULTIPLEXER fabricated with
silicon gate C
2
MOS technology. They achieve the high speed
operation similar to equivalent LSTTL while maintaining the
CMOS low power dissipation.
The TC74HC4051A has an 8 channel configuration, the
TC74HC4052A has a 4 channel × 2 configuration and the
TC74HC4053A has a 2 channel × 3 configuration.
The digital signal to the control terminal turns “ON” the
corresponding switch of each channel a large amplitude signal
(V
CC
−
V
EE
) can then be switched by the small logical amplitude
(V
CC
−
GND) control signal.
For example, in the case of V
CC
= 5 V, GND = 0 V, V
EE
=
−5
V,
signals between
−5
V and +5 V can be switched from the logical
circuit with a single power supply of 5 V. As the ON-resistance of
each switch is low, they can be connected to circuits with low
input impedance.
All inputs are equipped with protection circuits against static
discharge or transient excess voltage.
Note: xxxFN (JEDEC SOP) is not available in
Japan.
TC74HC4051AP, TC74HC4052AP,
TC74HC4053AP
TC74HC4051AF, TC74HC4052AF,
TC74HC4053AF
TC74HC4053AFN
Features
•
•
•
•
•
•
High speed: t
pd
=
15 ns (typ.) at V
CC
=
5 V, V
EE
=
0 V
Low power dissipation: I
CC
=
4
μA
(max) at Ta
=
25°C
High noise immunity: V
NIH
=
V
NIL
=
28% V
CC
(min)
Low ON resistance: R
ON
=
50
Ω
(typ.) at V
CC
−
V
EE
= 9 V
High noise immunity: THD
=
0.02% (typ.) at V
CC
−
V
EE
= 9 V
Pin and function compatible with 4051/4052/4053B
TC74HC4051AFT, TC74HC4052AFT,
TC74HC4053AFT
Weight
DIP16-P-300-2.54A
SOP16-P-300-1.27A
SOL16-P-150-1.27
TSSOP16-P-0044-0.65A
: 1.00 g (typ.)
: 0.18 g (typ.)
: 0.13 g (typ.)
: 0.06 g (typ.)
1
2007-10-01
TC74HC4051,4052AP/AF/AFT,4053AP/AF/AFN/AFT
Absolute Maximum Ratings (Note 1)
Characteristics
Supply voltage range
Supply voltage range
Control input voltage
Switch I/O voltage
Control input diode current
I/O diode current
Switch through current
DC V
CC
or ground current
Power dissipation
Storage temperature
Symbol
V
CC
V
CC
-V
EE
V
IN
V
I/O
I
ICK
I
OK
I
T
I
CC
P
D
T
stg
Rating
−
0.5 to 7
−
0.5 to 13
−
0.5 to V
CC
+
0.5
Unit
V
V
V
V
mA
mA
mA
mA
mW
°C
V
EE
−
0.5 to V
CC
+
0.5
±
20
±
20
±
25
±
50
500 (DIP) (Note 2)/180 (SOP, TSSOP)
−
65 to 150
Note 1: Exceeding any of the absolute maximum ratings, even briefly, lead to deterioration in IC performance or
even destruction.
Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the
significant change in temperature, etc.) may cause this product to decrease in the reliability significantly
even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute
maximum ratings and the operating ranges.
Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook
(“Handling Precautions”/“Derating Concept and Methods”) and individual reliability data (i.e. reliability test
report and estimated failure rate, etc).
Note 2: 500 mW in the range of Ta
= −40
to 65°C. From Ta
=
65 to 85°C a derating factor of
−10
mW/°C should be
applied up to 300 mW.
Operating Ranges (Note)
Characteristics
Supply voltage range
Supply voltage range
Supply voltage range
Control input voltage
Switch I/O voltage
Operating temperature
Symbol
V
CC
V
EE
V
CC
-V
EE
V
IN
V
I/O
T
opr
Rating
2 to 6
−
6 to 0
Unit
V
V
V
V
V
°C
2 to 12
0 to V
CC
V
EE
to V
CC
−
40 to 85
0 to 1000 (V
CC
=
2.0 V)
Control input rise and fall time
t
r
, t
f
0 to 500 (V
CC
=
4.5 V)
0 to 400 (V
CC
=
6.0 V)
ns
Note:
The operating ranges must be maintained to ensure the normal operation of the device.
Unused control inputs must be tied to either VCC or GND.
5
2007-10-01
PCB Design
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