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X98021L128-3.3-Z

Description
IC TRPL VID DIGITIZER 128MQFP
CategoryOther integrated circuit (IC)    Consumption circuit   
File Size1MB,29 Pages
ManufacturerRenesas Electronics Corporation
Websitehttps://www.renesas.com/
Environmental Compliance
Download Datasheet Parametric View All

X98021L128-3.3-Z Overview

IC TRPL VID DIGITIZER 128MQFP

X98021L128-3.3-Z Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
Parts packaging codeQFP
package instructionFQFP, QFP128,.67X.93,20
Contacts128
Reach Compliance Codecompliant
Factory Lead Time1 week
Commercial integrated circuit typesCONSUMER CIRCUIT
JESD-30 codeR-PQFP-G128
JESD-609 codee3
length20 mm
Humidity sensitivity level2A
Number of functions1
Number of terminals128
Maximum operating temperature70 °C
Minimum operating temperature
Package body materialPLASTIC/EPOXY
encapsulated codeFQFP
Encapsulate equivalent codeQFP128,.67X.93,20
Package shapeRECTANGULAR
Package formFLATPACK, FINE PITCH
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply3.3 V
Certification statusNot Qualified
Maximum seat height3.4 mm
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)3 V
surface mountYES
Temperature levelCOMMERCIAL
Terminal surfaceMatte Tin (Sn)
Terminal formGULL WING
Terminal pitch0.5 mm
Terminal locationQUAD
Maximum time at peak reflow temperatureNOT SPECIFIED
width14 mm
Base Number Matches1
X98021
NOT RECOMMENDED FOR NEW DESIGNS -
THE ISL98001-210 IS A 100% COMPATIBLE
IMPROVED ALTERNATIVE
DATASHEET
FN8219
Rev 3.00
March 8, 2006
210MHz Triple Video Digitizer with Digital PLL
The X98021 3-channel, 8-bit Analog Front End (AFE)
contains all the components necessary to digitize analog
RGB or YUV graphics signals from personal computers,
workstations and video set-top boxes. The fully differential
analog design provides high PSRR and dynamic
performance to meet the stringent requirements of the
graphics display industry. The AFE’s 210MSPS conversion
rate supports resolutions up to UXGA at 75Hz refresh rate,
while the front end's high input bandwidth ensures sharp
images at the highest resolutions.
To minimize noise, the X98021's analog section features 2
sets of pseudo-differential RGB inputs with programmable
input bandwidth, as well as internal DC restore clamping
(including mid-scale clamping for YUV signals). This is
followed by the programmable gain/offset stage and the
three 210MSPS Analog-to-Digital Converters (ADCs).
Automatic Black Level Compensation (ABLC™ eliminates
part-to-part offset variation, ensuring perfect black level
performance in every application.
The X98021's digital PLL generates a pixel clock from the
analog source's HSYNC or SOG (Sync-On-Green) signals.
Pixel clock output frequencies range from 10MHz to 210MHz
with sampling clock jitter of 250ps peak to peak.
Features
• 210MSPS maximum conversion rate
• Low PLL clock jitter (250ps p-p @ 210MSPS)
• 64 interpixel sampling positions
• 0.35V
p-p
to 1.4V
p-p
video input range
• Programmable bandwidth (100MHz to 780MHz)
• 2 channel input multiplexer
• RGB and YUV 4:2:2 output formats
• 5 embedded voltage regulators allow operation from
single 3.3V supply and enhance performance, isolation
• Completely independent 8 bit gain/10 bit offset control
• CSYNC and SOG support
• Trilevel sync detection
• 1.1W typical P
D
@ 210MSPS
• Pb-free plus anneal available (RoHS compliant)
Applications
• LCD Monitors and Projectors
• Digital TVs
• Plasma Display Panels
• RGB Graphics Processing
• Scan Converters
Simplified Block Diagram
RGB/YPbPr
IN
1
RGB/YPbPr
IN
2
3
3
Voltage
Clamp
PGA
+
Offset
DAC
ABLC™
8 or 16
8 bit ADC
x3
RGB/YUV
OUT
HSYNC
OUT
VSYNC
OUT
SOG
IN
1/2
HSYNC
IN
1/2
VSYNC
IN
1/2
Sync
Processing
Digital PLL
HS
OUT
PIXELCLK
OUT
AFE Configuration and Control
FN8219 Rev 3.00
March 8, 2006
Page 1 of 29

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