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FN7621
Rev 1.00
June 7, 2011
Dual PWM Controller For Powering AMD SVI Split-Plane Processors
The ISL6328 dual PWM controller delivers high efficiency and
tight regulation from two synchronous buck DC/DC converters.
The ISL6328 supports power control of AMD processors, which
operate from a serial VID interface (SVI). The dual output
ISL6328 features a multi-phase controller to support the Core
voltage (VDD) and a single phase controller to power the
Northbridge (VDDNB).
A precision core voltage regulation system is provided by a
one-to-four-phase PWM voltage regulator (VR) controller. The
integration of two power MOSFET drivers adds flexibility in
layout and reduces the number of external components in the
multi-phase section. A single phase PWM controller with
integrated driver provides a second precision voltage
regulation system for the Northbridge portion of the processor.
This monolithic, dual controller with an integrated driver
solution provides a cost and space saving power management
solution.
For applications that benefit from load line programming to
reduce bulk output capacitors, the ISL6328 features temperature
compensated output voltage droop. The multi-phase portion
also includes advanced control loop features for optimal
transient response to load application and removal. One of
these features is highly accurate, fully differential, continuous
DCR current sensing for load line programming and channel
current balance. Dual edge modulation is another unique
feature, allowing for quicker initial response to high di/dt load
transients.
The ISL6328 supports Power Savings Mode by dropping the
number of phases when the PSI_L bit is set.
Features
• Processor Core Voltage Via Integrated Multi-Phase Power
Conversion
• Configuration Flexibility
- 1 or 2-Phase Operation with Internal Drivers
- 3 or 4-Phase Operation with External PWM Drivers
• PSI_L Support
- Phase Shedding for Improved Efficiency at Light Load
- Diode Emulation in PSI mode
- Gate Voltage Optimization
• Precision Core Voltage Regulation
- Differential Remote Voltage Sensing
-
0.6%
System Accuracy Over-Temperature
• Optimal Processor Core Voltage Transient Response
- Adaptive Phase Alignment (APA)
- Active Pulse Positioning Modulation
• Fully Differential, Continuous DCR Current Sensing
- Accurate Load Line Programming
- Precision Channel Current Balancing
- Temperature Compensated
• Serial VID interface Handles up to 3.4MHz Clock Rates
• Two Level Overcurrent Protection Allows for High Current
Throttling (I
DD_SPIKE
)
• Multi-tiered Overvoltage Protection
• Selectable Switching Frequency up to 1MHz
• Simultaneous Digital Soft-Start of Both Outputs
FN7621 Rev 1.00
June 7, 2011
Page 1 of 33
ISL6328
Pin Configuration
ISL6328
(48 LD QFN)
TOP VIEW
PHASE_NB
38
UGATE_NB
LGATE_NB
ISEN_NB+
BOOT_NB
ISEN_NB-
ISEN4+
ISEN3+
ISEN4-
ISEN3-
48
COMP_NB
FB_NB
VSEN_NB
DRPCTRL
SVC
SVD
VCC
RSVD
OFS
OCP
TCOMP1
TCOMP2
1
2
3
4
5
6
7
8
9
10
11
12
13
RGND
47
46
45
44
43
42
41
40
39
37
36
35
34
33
32
PWM4
PWROK
VDDPWRGD
PHASE1
UGATE1
BOOT1
LGATE1
GVOT
LGATE2
BOOT2
UGATE2
EN
PWM3
31
30
29
28
27
26
25
24
PHASE2
49
GND
14
VSEN
15
FB_PSI
16
FB
17
COMP
18
FS
PVCC
19
APA
20
ISEN1+
21
ISEN1-
22
ISEN2+
23
ISEN2-
Functional Pin Descriptions
PIN NAME
COMP_NB
FB_NB
VSEN_NB
DRPCTRL
PIN NUMBER
1
2
3
4
DESCRIPTION
Output of the internal error amplifier for the Northbridge regulator.
Inverting input to the internal error amplifier for the Northbridge regulator.
Non-inverting input to the Northbridge regulator precision differential remote-sense amplifier. This pin
should be connected to the remote Northbridge sense pin of the processor, VDDNB_SENSE.
Droop Control for Core and Northbridge. This pin is used to set up one of four user programmable selections
via a resistor: Core Droop On and Northbridge Droop On; Core Droop Off and Northbridge Droop On, Core
Droop On and Northbridge Droop Off; Core Droop Off and Northbridge Droop Off.
If the resistor is tied to ground, the number of active phases in PSI mode is 1. If the resistor is tied to
VCC, the number of active phases in PSI mode is 2.
Serial VID clock input from the AMD processor.
Serial VID data bi-directional signal to and from the master device on AMD processor.
VCC is the bias supply for the ICs small-signal circuitry. Connect this pin to a +5V supply and decouple
using a quality 0.1µF ceramic capacitor.
RESERVED. Connect this pin directly to the VCC pin.
The OFS pin provides a means to program a DC current for generating an offset voltage across the resistor
between FB and VSEN. The offset current is generated via an external resistor and precision internal
voltage references. The polarity of the offset is selected by connecting the resistor to GND or VCC. For no
offset, the OFS pin should be left unconnected.
SVC
SVD
VCC
RSVD
OFS
5
6
7
8
9
FN7621 Rev 1.00
June 7, 2011
Page 5 of 33
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