LFSCM3GA80EP1-6FFN1704C datasheet, PDF

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LFSCM3GA80EP1-6FFN1704C: DescriptionIC FPGA 904 I/O 1704FCBGA; CategoryProgrammable logic devices Programmable logic; File Size3MB，244 Pages; ManufacturerLattice; Websitehttp://www.latticesemi.com; Environmental Compliance

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IC FPGA 904 I/O 1704FCBGA

LFSCM3GA80EP1-6FFN1704C Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Lattice
Parts packaging code	BGA
package instruction	42.5 X 42.5 MM, LEAD FREE, FCBGA-1704
Contacts	1704
Reach Compliance Code	not_compliant
ECCN code	EAR99
maximum clock frequency	1000 MHz
JESD-30 code	S-PBGA-B1704
length	42.5 mm
Configurable number of logic blocks	308
Equivalent number of gates	80000
Number of entries	904
Number of logical units	80100
Output times	904
Number of terminals	1704
Maximum operating temperature	70 °C
Minimum operating temperature
organize	308 CLBS, 80000 GATES
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Encapsulate equivalent code	BGA1704,42X42,40
Package shape	SQUARE
Package form	GRID ARRAY
power supply	1.2,1.2/3.3,2.5 V
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY
Certification status	Not Qualified
Maximum seat height	3.25 mm
Maximum supply voltage	1.26 V
Minimum supply voltage	0.95 V
Nominal supply voltage	1.2 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
width	42.5 mm

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LatticeSC/M Family Data Sheet

DS1004 Version 02.4, December 2011

LatticeSC/M Family Data Sheet

Architecture

December 2008

Data Sheet DS1004

Architecture Overview

The LatticeSC architecture contains an array of logic blocks surrounded by Programmable I/O Cells (PIC). Inter-

spersed between the rows of logic blocks are rows of sysMEM Embedded Block RAM (EBR). The upper left and

upper right corners of the devices contain SERDES blocks and their associated PCS blocks, as show in Figure 2-1.

Top left and top right corner of the device contain blocks of SERDES. Each block of SERDES contains four chan-

nels (quad). Each channel contains a single serializer and de-serializer, synchronization and word alignment logic.

The SERDES quad connects with the Physical Coding Sub-layer (PCS) blocks that contain logic to simultaneously

perform alignment, coding, de-coding and other functions. The SERDES quad block has separate supply, ground

and reference voltage pins.

The PICs contain logic to facilitate the conditioning of signals to and from the I/O before they leave or enter the

FPGA fabric. The block provides DDR and shift register capabilities that act as a gearbox between high speed I/O

and the FPGA fabric. The blocks also contain programmable Adaptive Input Logic that adjusts the delay applied to

signals as they enter the device to optimize setup and hold times and ensure robust performance.

sysMEM EBRs are large dedicated fast memory blocks. They can be configured as RAM, ROM or FIFO. These

blocks have dedicated logic to simplify the implementation of FIFOs.

The PFU, PIC and EBR blocks are arranged in a two-dimensional grid with rows and columns as shown in

Figure 2-1. These blocks are connected with many vertical and horizontal routing channel resources. The place

and route software tool automatically allocates these routing resources.

The corners contain the sysCLOCK Analog Phase Locked Loop (PLL) and Delay Locked Loop (DLL) Blocks. The

PLLs have multiply, divide and phase shifting capability; they are used to manage the phase relationship of the

clocks. The LatticeSC architecture provides eight analog PLLs per device and 12 DLLs. The DLLs provide a simple

delay capability and can also be used to calibrate other delays within the device.

Every device in the family has a JTAG Port with internal Logic Analyzer (ispTRACY) capability. The sysCONFIG™

port which allows for serial or parallel device configuration. The system bus simplifies the connections of the exter-

nal microprocessor to the device for tasks such as SERDES and PCS configuration or interface to the general

FPGA logic. The LatticeSC devices use 1.2V as their core voltage operation with 1.0V operation also possible.

or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

www.latticesemi.com

2-1

DS1004 A

rchitecture_02.0

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Description	IC FPGA 904 I/O 1704FCBGA	IC fpga 942 I/O 1704bga	IC fpga 660 I/O 1152bga	Board Connector, 6 Contact(s), 1 Row(s), Male, Right Angle, 0.1 inch Pitch, Solder Terminal, Black Insulator, Receptacle	IC fpga 904 I/O 1704bga	IC FPGA 904 I/O 1704FCBGA	Field Programmable Gate Array,
Reach Compliance Code	not_compliant	_compli	_compli	unknown	not_compliant	not_compliant	compliant
ECCN code	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99
Is it Rohs certified?	conform to	conform to	conform to	incompatible	conform to	incompatible	-
Maker	Lattice	Lattice	Lattice	-	Lattice	Lattice	Lattice
Parts packaging code	BGA	BGA	BGA	-	BGA	BGA	-
package instruction	42.5 X 42.5 MM, LEAD FREE, FCBGA-1704	42.5 X 42.5 MM, LEAD FREE, FCBGA-1704	35 X 35 MM, LEAD FREE, FCBGA-1152	-	42.5 X 42.5 MM, LEAD FREE, FCBGA-1704	BGA, BGA1704,42X42,40	,
Contacts	1704	1704	1152	-	1704	1704	-
maximum clock frequency	1000 MHz	1000 MHz	1000 MHz	-	1000 MHz	1000 MHz	-
JESD-30 code	S-PBGA-B1704	S-PBGA-B1704	S-PBGA-B1152	-	S-PBGA-B1704	S-CBGA-B1704	-
length	42.5 mm	42.5 mm	35 mm	-	42.5 mm	42.5 mm	-
Configurable number of logic blocks	308	424	424	-	308	308	-
Equivalent number of gates	80000	115000	115000	-	80000	80000	-
Number of entries	904	942	660	-	904	904	-
Number of logical units	80100	115200	115200	-	80100	80100	-
Output times	904	942	660	-	904	904	-
Number of terminals	1704	1704	1152	-	1704	1704	-
Maximum operating temperature	70 °C	85 °C	85 °C	125 °C	85 °C	70 °C	-
Minimum operating temperature	-	-40 °C	-40 °C	-40 °C	-40 °C	-	-
organize	308 CLBS, 80000 GATES	424 CLBS, 115000 GATES	424 CLBS, 115000 GATES	-	308 CLBS, 80000 GATES	308 CLBS, 80000 GATES	-
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	-	PLASTIC/EPOXY	CERAMIC, METAL-SEALED COFIRED	-
encapsulated code	BGA	BGA	BGA	-	BGA	BGA	-
Encapsulate equivalent code	BGA1704,42X42,40	BGA1704,42X42,40	BGA1152,34X34,40	-	BGA1704,42X42,40	BGA1704,42X42,40	-
Package shape	SQUARE	SQUARE	SQUARE	-	SQUARE	SQUARE	-
Package form	GRID ARRAY	GRID ARRAY	GRID ARRAY	-	GRID ARRAY	GRID ARRAY	-
power supply	1.2,1.2/3.3,2.5 V	1.2,1.2/3.3,2.5 V	1.2,1.2/3.3,2.5 V	-	1.2,1.2/3.3,2.5 V	1.2,1.2/3.3,2.5 V	-
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY	FIELD PROGRAMMABLE GATE ARRAY	FIELD PROGRAMMABLE GATE ARRAY	-	FIELD PROGRAMMABLE GATE ARRAY	FIELD PROGRAMMABLE GATE ARRAY	FIELD PROGRAMMABLE GATE ARRAY
Certification status	Not Qualified	Not Qualified	Not Qualified	-	Not Qualified	Not Qualified	-
Maximum seat height	3.25 mm	3.25 mm	3.5 mm	-	3.25 mm	5.3 mm	-
Maximum supply voltage	1.26 V	1.26 V	1.26 V	-	1.26 V	1.26 V	-
Minimum supply voltage	0.95 V	0.95 V	0.95 V	-	0.95 V	0.95 V	-
Nominal supply voltage	1.2 V	1.2 V	1.2 V	-	1.2 V	1.2 V	-
surface mount	YES	YES	YES	-	YES	YES	-
technology	CMOS	CMOS	CMOS	-	CMOS	CMOS	-
Temperature level	COMMERCIAL	INDUSTRIAL	INDUSTRIAL	-	INDUSTRIAL	COMMERCIAL	-
Terminal form	BALL	BALL	BALL	-	BALL	BALL	-
Terminal pitch	1 mm	1 mm	1 mm	2.54 mm	1 mm	1 mm	-
Terminal location	BOTTOM	BOTTOM	BOTTOM	-	BOTTOM	BOTTOM	-
width	42.5 mm	42.5 mm	35 mm	-	42.5 mm	42.5 mm	-

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