EZR32HG Wireless MCUs
EZR32HG320 Data Sheet
EZR32HG320 Wireless MCU family with ARM Cortex-M0+ CPU,
USB, and sub-GHz Radio
The EZR32HG Wireless MCUs are the latest in Silicon Labs family of wireless MCUs
delivering a high performance, low-energy wireless solution integrated into a small form
factor package. By combining a high performance sub-GHz RF transceiver with an ener-
gy efficient 32-bit MCU, the EZR32HG family provides designers the ultimate in flexibility
with a family of pin-compatible devices that scale with 64/32 kB of flash and support Sili-
con Labs EZRadio or EZRadioPRO transceivers. The ultra-low power operating modes
and fast wake-up times of the Silicon Labs energy friendly 32-bit MCUs, combined with
the low transmit and receive power consumption of the sub-GHz radio, result in a solu-
tion optimized for battery powered applications.
32-Bit ARM Cortex wireless MCUs applications include the following:
• Energy, gas, water and smart metering
• Health and fitness applications
• Consumer electronics
• Alarm and security systems
• Building and home automation
KEY FEATURES
• Silicon Labs’ energy efficient 32-bit
Wireless MCUs
• Based on ARM Cortex M0 CPU core with
64 kB of flash and 8 kB RAM
• Best-in-class RF performance with EZradio
and EZRadioPro transceivers
• Ultra-low power wireless MCU
• Low transmit and receive currents
• Ultra-low power standby and sleep
modes
• Fast wake-up time
• Rich set of peripherals including 12-bit ADC
and IDAC, multiple communication
interfaces (USB, UART, SPI, I2C), multiple
GPIO and timers
• AES Accelerator with 128-bit keys
EZR32HG320 F64/F32
Core and Memory
ARM Cortex™ M0+ processor
Clock Management
Energy Management
Voltage
Regulator
Brown-out
Detector
Voltage
Comparator
Power-on
Reset
Security
Hardware
AES
Flash
Program
Memory
RAM
Memory
Debug
Interface
w/ MTB
DMA
Controller
32-bit bus
Peripheral Reflex System
Transceiver
TX 18 mA
@ +10 dBm
RX 10 mA
Preamble
Sense 6.0 mA
142-1050
MHz
ASK, OOK
G(FSK)
4(G)FSK
SPI
Serial Interfaces
USART
IC
Low
Energy
USB
2
I/O Ports
External
Interrupts
Pin
Reset
General
Purpose
I/O
Pin
Wakeup
Timers and Triggers
Timer/
Counter
Pulse
Counter
Real Time
Counter
Watchdog
Timer
Analog Interfaces
ADC
1 Mbps
SPI
Low
Energy
UART™
Current
DAC
Antenna
Diversity
133 dBm
sensitivity
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EZR32HG320 Data Sheet
Feature List
1. Feature List
The HG highlighted features are listed below.
MCU Features
• ARM Cortex-M0+ CPU platform
• Up to 25 MHz
• 64/32 kB Flash w/8 kB RAM
• Hardware AES with 128-bit keys
• Flexible Energy Management System
• 20 nA @ 3 V Shutoff Mode
• 0.6 µA @ 3 V Stop Mode
• 127 µA/MHz @ 3 V Run Mode
• Timers/Counters
• 3× Timer/Counter
• 3×3 Compare/Capture/PWM channels
• Real-Time Counter
• 16/8-bit Pulse Counter
• Watchdog Timer
• Communication interfaces
• 1× USART (UART/SPI)
• 1× Low Energy UART
• 1× I2C Interface with SMBus support
• Universal Serial Bus (USB)
• Ultra low power precision analog peripherals
• 12-bit 1 Msamples/s ADC
• On-chip temperature sensor
• Current Digital to Analog Converter
• Up to 25 General Purpose I/O pins
RF Features
• Frequency Range
• 142-1050 MHz
• Modulation
• (G)FSK, 4(G)FSK, (G)MSK, OOK
• Receive sensitivity up to -133 dBm
• Up to +20 dBm max output power
• Low active power consumption
• 10/13 mA RX
• 18 mA TX at +10 dBm
• 6 mA @ 1.2 kbps (Preamble Sense)
• Data rate = 100 bps to 1 Mbps
• Excellent selectivity performance
• 69 dB adjacent channel
• 79 dB blocking at 1 MHz
• Antenna diversity and T/R switch control
• Highly configurable packet handler
• TX and RX 64 byte FIFOs
• Automatic frequency control (AFC)
• Automatic gain control (AGC)
• IEEE 802.15.4g compliant
System Features
•
•
•
•
•
Power-on Reset and Brown-Out Detector
Debug Interface
Temperature range -40 to 85 °C
Single power supply 1.98 to 3.8 V
QFN48 package
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EZR32HG320 Data Sheet
Ordering Information
2. Ordering Information
The table below shows the available EZR32HG320 devices.
Table 2.1. Ordering Information
Ordering
EZR32HG320FxxR55G-B0
EZR32HG320FxxR60G-B0
EZR32HG320FxxR61G-B0
EZR32HG320FxxR63G-B0
EZR32HG320FxxR67G-B0
EZR32HG320FxxR68G-B0
EZR32HG320FxxR69G-B0
Radio
EZRadio
EZRadioPro
EZRadioPro
EZRadioPro
EZRadioPro
EZRadioPro
EZRadioPro
Flash (kB)
32-64
32-64
32-64
32-64
32-64
32-64
32-64
RAM (kB)
8
8
8
8
8
8
8
Power Am- Max Sensi-
plifier (dBm) tivity (dBm)
+13
+13
+16
+20
+13
+20
+13 & 20
-116
-126
-126
-126
-133
-133
-133
Supply Volt-
age (V)
1.98 - 3.8
1.98 - 3.8
1.98 - 3.8
1.98 - 3.8
1.98 - 3.8
1.98 - 3.8
1.98 - 3.8
Package
QFN48
QFN48
QFN48
QFN48
QFN48
QFN48
QFN48
Table 2.2. Flash Sizes
Example Part Number
EZR32HG320F32R55G
EZR32HG320F64R55G
Note:
Add an "(R)" at the end of the device part number to denote tape and reel option.
Visit
www.silabs.com
for information on global distributors and representatives.
Flash Size
32 kB
64 kB
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EZR32HG320 Data Sheet
System Overview
3. System Overview
3.1 Introduction
The EZR32HG320 Wireless MCUs are the latest in the Silicon Labs family of wireless MCUs delivering a high-performance, low-energy
wireless solution integrated into a small form factor package. By combining a high performance sub-GHz RF transceiver with an energy
efficient 32-bit ARM Cortex-M0+, the EZR32HG family provides designers with the ultimate in flexibility with a family of pin-compatible
parts that scale from 32 to 64 kB of flash and support Silicon Labs EZRadio or EZRadioPRO transceivers. The ultra-low power operat-
ing modes and fast wake-up times combined with the low transmit and receive power consumption of the sub-GHz radio result in a
solution optimized for low power and battery powered applications. For a complete feature set and in-depth information on the modules,
the reader is referred to the
EZR32HG Reference Manual.
The EZR32HG320 block diagram is shown below.
EZR32HG320 F64/F32
Core and Memory
ARM Cortex™ M0+ processor
Clock Management
Energy Management
Voltage
Regulator
Brown-out
Detector
Voltage
Comparator
Power-on
Reset
Security
Hardware
AES
Flash
Program
Memory
RAM
Memory
Debug
Interface
w/ MTB
DMA
Controller
32-bit bus
Peripheral Reflex System
Transceiver
TX 18 mA
@ +10 dBm
RX 10 mA
Preamble
Sense 6.0 mA
142-1050
MHz
ASK, OOK
G(FSK)
4(G)FSK
SPI
Serial Interfaces
USART
IC
Low
Energy
USB
2
I/O Ports
External
Interrupts
Pin
Reset
General
Purpose
I/O
Pin
Wakeup
Timers and Triggers
Timer/
Counter
Pulse
Counter
Real Time
Counter
Watchdog
Timer
Analog Interfaces
ADC
1 Mbps
SPI
Low
Energy
UART™
Current
DAC
Antenna
Diversity
133 dBm
sensitivity
Figure 3.1. Block Diagram
3.1.1 ARM Cortex-M0+ Core
The ARM Cortex-M0+ includes a 32-bit RISC processor which can achieve as much as 0.9 Dhrystone MIPS/MHz. A Wake-up Interrupt
Controller handling interrupts triggered while the CPU is asleep is included as well. The EZR32 implementation of the Cortex-M0+ is
described in detail in
ARM Cortex-M0+ Devices Generic User Guide.
3.1.2 Debugging Interface (DBG)
These devices include hardware debug support through a 2-pin serial-wire debug interface.
3.1.3 Memory System Controller (MSC)
The Memory System Controller (MSC) is the program memory unit of the EZR32HG microcontroller. The flash memory is readable and
writable from both the Cortex-M0+ and DMA. The flash memory is divided into two blocks: the main block and the information block.
Program code is normally written to the main block. Additionally, the information block is available for special user data and flash lock
bits. There is also a read-only page in the information block containing system and device calibration data. Read and write operations
are supported in the energy modes EM0 and EM1.
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EZR32HG320 Data Sheet
System Overview
3.1.4 Direct Memory Access Controller (DMA)
The Direct Memory Access (DMA) controller performs memory operations independently of the CPU. This has the benefit of reducing
the energy consumption and the workload of the CPU, and enables the system to stay in low energy modes when moving, for instance,
data from the USART to RAM or from the External Bus Interface to a PWM-generating timer. The DMA controller uses the PL230
µDMA controller licensed from ARM.
3.1.5 Reset Management Unit (RMU)
The Reset Management Unit (RMU) is responsible for handling the reset functionality of the EZR32HG.
3.1.6 Energy Management Unit (EMU)
The Energy Management Unit (EMU) manages all the low energy modes (EM) in EZR32HG microcontrollers. Each energy mode man-
ages if the CPU and the various peripherals are available. The EMU can also be used to turn off the power to unused SRAM blocks.
3.1.7 Clock Management Unit (CMU)
The Clock Management Unit (CMU) is responsible for controlling the oscillators and clocks on-board the EZR32HG. The CMU provides
the capability to turn on and off the clock on an individual basis to all peripheral modules in addition to enable/disable and configure the
available oscillators. The high degree of flexibility enables software to minimize energy consumption in any specific application by not
wasting power on peripherals and oscillators that are inactive.
3.1.8 Watchdog (WDOG)
The purpose of the watchdog timer is to generate a reset in case of a system failure, to increase application reliability. The failure may,
for example, be caused by an external event, such as an ESD pulse, or by a software failure.
3.1.9 Peripheral Reflex System (PRS)
The Peripheral Reflex System (PRS) system is a network which lets the different peripheral module communicate directly with each
other without involving the CPU. Peripheral modules which send out Reflex signals are called producers. The PRS routes these reflex
signals to consumer peripherals which apply actions depending on the data received. The format for the Reflex signals is not given, but
edge triggers and other functionality can be applied by the PRS.
3.1.10 Universal Serial Bus Controller (USB)
The USB is a full-speed USB 2.0 compliant device controller. The device supports both fullspeed (12 MBit/s) and low speed (1.5 MBit/s)
operation. The USB also supports a Low Energy Mode that can be used to lower the current consumption up to 90% by shutting off the
clock to the USB Core adn possibly suspending the USHFRCO. The USB device includes an internal dedicated Descriptor-Based Scat-
ter/Garther DMA and supports up to 3 OUT endpoints and 3 IN endpoints, in addition to endpoint 0.
3.1.11 Inter-Integrated Circuit Interface (I
2
C)
The I
2
C module provides an interface between the MCU and a serial I
2
C-bus. It is capable of acting as both a master and a slave, and
supports multi-master buses. Both standard-mode, fast-mode and fast-mode plus speeds are supported, allowing transmission rates all
the way from 10 kbit/s up to 1 Mbit/s. Slave arbitration and timeouts are also provided to allow implementation of an SMBus compliant
system. The interface provided to software by the I
2
C module allows both fine-grained control of the transmission process and close to
automatic transfers. Automatic recognition of slave addresses is provided in all energy modes.
3.1.12 Universal Synchronous/Asynchronous Receiver/Transmitter (USART)
The Universal Synchronous Asynchronous serial Receiver and Transmitter (USART) is a very flexible serial I/O module. It supports full
duplex asynchronous UART communication as well as RS-485, SPI, MicroWire and 3-wire. It can also interface with ISO7816 Smart-
Cards, IrDA and I2S devices.
3.1.13 Pre-Programmed USB/UART Bootloader
The bootloader presented in application note
AN0042
is pre-programmed in the device at the factory. The bootloader enables users to
program the EZR32 through a UART or a USB CDC class virtual UART without the need for a debuger. The autobaud feature, inter-
face, and commands are described further in the application note.
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