ATECC108-MAHDA-T datasheet, PDF

Datasheet> All Categories > semiconductor> Other integrated circuit (IC)> ATECC108-MAHDA-T

ATECC108-MAHDA-T: DescriptionIC AUTHENTICATION CHIP 8UDFN; Categorysemiconductor Other integrated circuit (IC); File Size382KB，11 Pages; ManufacturerMicrochip; Websitehttps://www.microchip.com; Environmental Compliance

Download Datasheet Parametric Compare View All

ATECC108-MAHDA-T Online Shopping

Suppliers	Part Number	Price	MOQ	In stock
	ATECC108-MAHDA-T	-	-	View	Buy Now

ATECC108-MAHDA-T Overview

IC AUTHENTICATION CHIP 8UDFN

ATECC108-MAHDA-T Parametric

Parameter Name	Attribute value
type	Verification chip
application	Networking and Communications
Installation type	surface mount
Package/casing	8-UFDFN exposed pad
Supplier device packaging	8-UDFN（2x3）

Preview

Download Datasheet

View All

ATECC108

Atmel CryptoAuthentication

NOT RECOMMENDED

FOR NEW DESIGNS

SUMMARY DATASHEET

Features



Replaced by

ATECC108A

Secure authentication and product validation device

High-Speed Public Key Algorithm (PKI) Crypto Engine

FIPS186-3 Elliptic Curve Digital Signature Algorithm (ECDSA)

NIST Standard P256, B283, and K283 Elliptic Curve support

Superior SHA-256 Hash Algorithm; HMAC option

Integrated capability for both Host and Client operations

Best in class 256/283-bit key length, storage for up to 16 keys

Guaranteed unique 72-bit serial number

Internal high-quality FIPS Random Number Generator (RNG)

8.5Kb EEPROM memory for keys, certificates, and data

512 One Time Programmable (OTP) bits for fixed information or

consumption logging

Multiple I/O options

High-Speed single pin interface, with one GPIO pin

1MHz standard I

C interface



Integrated temperature sensor

Uncalibrated accuracy, -40C to +85C (±3C)

2.0V – 5.5V supply voltage range

1.8V – 5.5V communications

<150nA sleep current

Extended multi-level hardware security

8-lead SOIC, 8-pad UDFN, and 3-lead CONTACT packages

Applications



Anti-clone for accessories, daughter cards, and consumables

Secure boot validation — software anti-piracy

Network and computer access control and password handling

Authenticated/encrypted network communications

This is a summary document.

The complete document is

available under NDA. For more

information, please contact

your local Atmel sales office.

Atmel-8873BS-CryptoAuth-ATECC108-Datasheet-Summary_102013

1.1

Introduction

Applications

The Atmel

ATECC108 is a member of the Atmel CryptoAuthentication

™

family of high-security hardware

authentication devices. It has a flexible command set that allows use for many applications, including the following:



Anti-Counterfeiting —

Validates that a removable, replaceable, or consumable client is authentic.

Examples of clients could be system accessories, electronic daughter cards, or other spare parts. It can also

be used to validate a software/firmware module or memory storage element.



Protection for Firmware or Media —

Validate code stored in flash memory at boot to prevent unauthorized

modifications, encrypt downloaded program files as a common broadcast, or uniquely encrypt code images

to be usable on a single system only.



Secure Data Storage —

Store secret keys for use by crypto accelerators in standard microprocessors.

ATECC108 can also be used to store small quantities of data necessary for configuration, calibration, ePurse

value, consumption data, or other secrets. Programmable protection is available using

encrypted/authenticated reads and writes.



User Password Checking —

Validates user entered passwords without letting the expected value become

known, map memorable passwords to random number, and securely exchange password values with

remote system.

1.2

Device Features

ATECC108 includes an EEPROM array that can be used for storage of up to 16 keys, miscellaneous read/write,

read-only or secret data, consumption logging, and security configuration. Access to the various sections of

memory can be restricted in a variety of ways and then the configuration locked to prevent changes.

ATECC108 features a wide array of defensive mechanisms specifically designed to prevent physical attacks on the

device itself or logical attacks on the data transmitted between the device and the system. Hardware restrictions on

the ways in which keys are used or generated provide further defense against certain styles of attack.

Access to the device is through a standard I

C Interface at speeds up to 1Mb/sec. It is compatible with standard

Serial EEPROM I

C interface specifications. The device also supports a Single-Wire Interface that can reduce the

number of GPIOs required on the system processor and/or reduce the number of pins on connectors. Additionally,

the device supports an alternative Single-Wire Interface compatible with other single-wire devices. If either Single-

Wire Interface is enabled, the remaining pin is available for use as a GPIO. Contact Atmel for more details.

Using either the I

C or Single-Wire Interface, multiple ATECC108 devices can share the same bus which saves

processor GPIO usage in system with multiple clients such as different color ink tanks or multiple spare parts.

Each ATECC108 ships with a guaranteed unique 72-bit serial number. Using the cryptographic protocols

supported by the device, a Host system or remote server can verify a signature to prove that the serial number is

both authentic and not a copy. Serial numbers are often stored in a standard Serial EEPROM but these can be

easily copied, and there is no way for the Host to know if the serial number is authentic or if it's a clone.

ATECC108 can generate high-quality FIPS random numbers and employ them for any purpose, including usage

as part of the device’s crypto protocols. Because each random number is guaranteed to be essentially unique from

all numbers ever generated on this or any other device, their inclusion in the protocol calculation ensures that

replay attacks (re-transmitting a previously successful transaction) always fails.

System integration is eased with a wide supply voltage range (2.0V – 5.5V) and an ultra-low sleep current of

<150nA.

ATECC108 [SUMMARY DATASHEET]

Atmel-8873BS-CryptoAuth-ATECC108-Datasheet-Summary_102013

1.3

Cryptographic Operation

ATECC108 implements a complete asymmetric (public/private) key cryptographic signature solution based on

Elliptic Curve Cryptography and the ECDSA signature protocol. The device features hardware acceleration for the

NIST standard P256, B283, and K283 binary curves and supports the complete key life cycle from high quality

private key generation, ECDSA signature generation and public key signature verification. The hardware

accelerator can implement these asymmetric cryptographic operations 10 to 1,000 times faster than software

running on standard microprocessors without the usual high risk of key exposure.

The device is designed to be able to securely store multiple private keys along with their public keys and the

signature components of the corresponding certificates. The signature verification command can use any stored or

external ECC public key. Public keys stored within the device can be configured to require validation via a

certificate chain to speed up future device authentication.

Random private key generation is supported internally within the device to ensure that the private key can never be

known outside the device. The public key corresponding to a stored private key is always returned when the key is

generated and may optionally be computed at a later time.

ATECC108 also supports a standard hash-based challenge response protocol to simplify programming. At its most

basic, the system sends a challenge to the device which combines that challenge with a secret key via the

MAC

command from the system, and sends the response back to the system. The device uses a

SHA-256 cryptographic hash algorithm for the combination such that an observer on the bus cannot derive the

value of the secret key, but the recipient can verify that the response is correct by performing the same calculation

with a stored copy of the secret.

Due to the flexible command set of the ATECC108, these two basic operation sets (ECDSA signatures and SHA-

256 challenge-response) can be expanded in many ways. Using the

GenDig

command, the values in other slots

can be included in the response digest or signature, which provides an effective way of proving that a data read

really did come from the device, as opposed to being inserted by a man-in-the-middle attacker. This same

command can be used to combine two keys with the challenge, which is useful when there are multiple layers of

authentication to be performed.

The

DeriveKey

command implements a key rolling scheme. Depending on the command mode parameter, the

resulting operation can be similar to that implemented in a remote-controlled garage door opener. Each time the

key is used, the current value of the key is cryptographically combined with a value specific to that system, and the

result forms the key for the next cryptographic operation. Even if an attacker gets the value of one key, with the

next use, that key will be gone forever.

The

DeriveKey

command can also be used to generate new random keys that might be valid only for a particular

Host ID, for a particular time period, or for some other restricted environment. Each generated key is different than

any other key ever generated on any device. By activating a Host-Client pair in the field in this manner, a clone of a

single client will not work on any other Host.

In a Host-Client configuration, where the Host (for instance a mobile phone) needs to verify a client (for instance an

OEM battery), there is a need to store the secret in the Host in order to validate the response from the client. The

CheckMac

command allows the device to securely store the secret in the Host system and hides the correct

response value from the pins, returning only a

yes

answer to the system.

Where a user entered password is required, the

CheckMac

command also provides a way to both verify the

password without exposing it on the communications bus, as well as, mapping the password into a stored value

that can have a much higher entropy.

Finally, the hash combination of a challenge and secret key can be kept on the device and XOR’d with the contents

of a slot to implement an encrypted

Read

command, or it can be XOR’d with encrypted input data to implement an

encrypted

Write

command.

All hashing functions are implemented using the industry-standard SHA-256 secure hash algorithm, which is part

of the latest set of high-security cryptographic algorithms recommended by various governments and

cryptographic experts. If desired, the SHA-256 algorithm can also be included in a HMAC sequence. ATECC108

employs full-sized 256 bit secret keys to prevent any kind of exhaustive attack.

ATECC108 [SUMMARY DATASHEET]

Atmel-8873BS-CryptoAuth-ATECC108-Datasheet-Summary_102013

ATECC108-MAHDA-T Related Products

	ATECC108-MAHDA-T	ATECC108-SSHCZ-B	ATECC108-RBHCZ-T	ATECC108-MAHCZ-T	ATECC108-SSHCZ-T	ATECC108-SSHDA-T
Description	IC AUTHENTICATION CHIP 8UDFN	EEPROM Crypto Products, ECC 8kb	EEPROM Crypto Products, ECC 8kb	IC AUTHENTICATION CHIP 8UDFN	IC AUTHENTICATION CHIP 8SOIC	IC AUTHENTICATION CHIP 8SOIC
type	Verification chip	-	-	Verification chip	Verification chip	Verification chip
application	Networking and Communications	-	-	Networking and Communications	Networking and Communications	Networking and Communications
Installation type	surface mount	-	-	surface mount	surface mount	surface mount
Package/casing	8-UFDFN exposed pad	-	-	8-UFDFN exposed pad	8-SOIC (0.154", 3.90mm wide)	8-SOIC (0.154", 3.90mm wide)
Supplier device packaging	8-UDFN（2x3）	-	-	8-UDFN（2x3）	8-SOIC	8-SOIC

Recommended Resources

Application circuit of LM1876

Circuit Diagram 2 for Expanding the Output Capacity of the Power Transformer

Emitter amplitude modulation circuit

Power supply circuit diagram of EMC EM-1 color display

High input voltage integrated regulated power supply circuit composed of BG602 Part 2

Soft switching circuit schematic diagram

712 main frequency time problem, why interrupt processing time has not improved: The size of the external interrupt handler is more than 100 assembly instructions. In order to ensure the shortest interrupt processing time, 48 MHz main frequency is used, but it still takes a lot of...; 小庞 stm32/stm8

Can UART5 of STM32F103VCT6 use DMA?: As the title says, UART1-4 all have corresponding DMA channels, but UART5 does not have one. So I'm wondering if it's missing from the manual or if it just doesn't exist?...; qqq147258 stm32/stm8

Design Technology of Single-Chip Computer Power Supply: Abstract: This paper introduces the design ideas and methods of system power supply based on M6800 series microcontrollers, as well as the methods to eliminate the power frequency interference which h...; zbz0529 Power technology

Ask about PDIUSBD12 enumeration problem: I have a question for you! I am using PDIUSBD12 and connecting to the host through SoftConnect. The host displays "Unrecognized USB Device". Then the microcontroller program receives a reset signal an...; 孤帆 Embedded System

Network transmission between LPC1768 development boards: In view of the fact that the previous network topic posts were all about the communication between the computer and the development board, and there are relatively few communication routines between d...; jeansonm MCU

How to deal with large humidity error of HDC1008?: When I was using TI HDC1008, I found that the RH data (currently 200pcs) was 6%~7% higher, which exceeded the 4% accuracy claimed in its specification. The reason for the high accuracy is not clear ye...; majieno1 TI Technology Forum

Shortcut: E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF EG EH EI EJ EK EL EM EN EO EP EQ ER ES ET EU EV EW EX EY EZ F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF FG FH FI FJ FK FL FM FN FO FP FQ FR FS FT FU FV FW FX FY FZ G0 G1 G2 G3 G4 G5 G6 G7 G8 G9 GA GB GC GD GE GF GG GH GI GJ GK GL GM GN GO GP GQ GR GS GT GU GV GW GX GZ H0 H1 H2 H3 H4 H5 H6 H7 H8 HA HB HC HD HE HF HG HH HI HJ HK HL HM HN HO HP HQ HR HS HT HU HV HW HX HY HZ I1 I2 I3 I4 I5 I6 I7 IA IB IC ID IE IF IG IH II IK IL IM IN IO IP IQ IR IS IT IU IV IW IX J0 J1 J2 J6 J7 JA JB JC JD JE JF JG JH JJ JK JL JM JN JP JQ JR JS JT JV JW JX JZ K0 K1 K2 K3 K4 K5 K6 K7 K8 K9 KA KB KC KD KE KF KG KH KI KJ KK KL KM KN KO KP KQ KR KS KT KU KV KW KX KY KZ

Popular Components