BLC9G20LS-361AVT
Power LDMOS transistor
Rev. 3 — 24 November 2017
Product data sheet
1. Product profile
1.1 General description
360 W LDMOS packaged asymmetric Doherty power transistor for base station
applications at frequencies from 1805 MHz to 1990 MHz.
Table 1.
Typical performance
Typical RF performance at T
case
= 25
C in an asymmetrical Doherty demo circuit. V
DS
= 28 V;
I
Dq
= 400 mA (main); V
GS(amp)peak
= 0.7 V, unless otherwise specified.
Test signal
1-carrier W-CDMA
[1]
f
(MHz)
1805 to 1880
V
DS
(V)
28
P
L(AV)
(dBm)
47.8
G
p
(dB)
16.4
D
(%)
50
ACPR
(dBc)
30
[1]
Test signal: 3GPP test model 1; 64 DPCH; PAR = 7.2 dB at 0.01% probability on CCDF per carrier.
Table 2.
Typical performance
Typical RF performance at T
case
= 25
C in an asymmetrical Doherty demo circuit. V
DS
= 28 V;
I
Dq
= 450 mA (main); V
GS(amp)peak
= 0.6 V, unless otherwise specified.
Test signal
1-carrier W-CDMA
[1]
f
(MHz)
1930 to 1990
V
DS
(V)
28
P
L(AV)
(dBm)
47.8
G
p
(dB)
16.6
D
(%)
47.5
ACPR
(dBc)
35
[1]
Test signal: 3GPP test model 1; 64 DPCH; PAR = 7.2 dB at 0.01% probability on CCDF per carrier.
1.2 Features and benefits
Excellent ruggedness
High efficiency
Low thermal resistance providing excellent thermal stability
Designed for broadband operation (1805 MHz to 1990 MHz)
Asymmetric design to achieve optimum efficiency across the band
Lower output capacitance for improved performance in Doherty applications
Designed for low memory effects providing excellent digital pre-distortion capability
Internally matched for ease of use
Integrated ESD protection
Compliant to Directive 2002/95/EC, regarding Restriction of Hazardous Substances
(RoHS)
1.3 Applications
RF power amplifiers for base stations and multi carrier applications in the 1805 MHz to
1990 MHz frequency range
BLC9G20LS-361AVT
Power LDMOS transistor
2. Pinning information
Table 3.
Pin
1
2
3
4
5
6
7
[1]
Pinning
Description
drain2 (peak)
drain1 (main)
gate1 (main)
gate2 (peak)
source
video decoupling (peak)
video decoupling (main)
1, 6
aaa-014884
Simplified outline
7
2
1
6
5
Graphic symbol
2, 7
3
3
[1]
4
5
4
Connected to flange.
3. Ordering information
Table 4.
Ordering information
Package
Name Description
BLC9G20LS-361AVT
-
air cavity plastic earless flanged package; 6 leads
Version
SOT1258-1
Type number
4. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
V
DS
V
GS(amp)main
V
GS(amp)peak
T
stg
T
j
[1]
Parameter
drain-source voltage
main amplifier gate-source voltage
peak amplifier gate-source voltage
storage temperature
junction temperature
Conditions
Min
-
5
5
65
[1]
Max
65
+13
+13
+150
225
Unit
V
V
V
C
C
-
Continuous use at maximum temperature will affect the reliability, for details refer to the online MTF
calculator.
5. Thermal characteristics
Table 6.
R
th(j-c)
Thermal characteristics
Conditions
V
DS
= 28 V; I
Dq
= 400 mA (main);
V
GS(amp)peak
= 0.5 V; T
case
= 80
C
P
L
= 47.5 dBm
P
L
= 49.5 dBm
0.26
0.19
K/W
K/W
Typ
Unit
thermal resistance from junction
to case
Symbol Parameter
BLC9G20LS-361AVT
All information provided in this document is subject to legal disclaimers.
© Ampleon Netherlands B.V. 2017. All rights reserved.
Product data sheet
Rev. 3 — 24 November 2017
2 of 13
BLC9G20LS-361AVT
Power LDMOS transistor
6. Characteristics
Table 7.
DC characteristics
T
j
= 25
C unless otherwise specified.
Symbol
Parameter
Conditions
Min
65
1.5
-
-
-
-
-
Typ
-
2.0
-
26
-
1.27
120
Max
-
2.5
2.85
2.8
-
280
-
198
Unit
V
V
V
A
A
nA
S
m
Main device
V
(BR)DSS
drain-source breakdown voltage V
GS
= 0 V; I
D
= 1.2 mA
V
GS(th)
V
GSq
I
DSS
I
DSX
I
GSS
g
fs
R
DS(on)
gate-source threshold voltage
gate-source quiescent voltage
drain leakage current
drain cut-off current
gate leakage current
forward transconductance
drain-source on-state
resistance
V
DS
= 10 V; I
D
= 120 mA
V
DS
= 28 V; I
D
= 400 mA
V
GS
= 0 V; V
DS
= 32 V
V
GS
= V
GS(th)
+ 3.75 V;
V
DS
= 10 V
V
GS
= 11 V; V
DS
= 0 V
V
DS
= 10 V; I
D
= 0.12 A
V
GS
= V
GS(th)
+ 3.75 V;
I
D
= 4.2 A
1.65 2.25
Peak device
V
(BR)DSS
drain-source breakdown voltage V
GS
= 0 V; I
D
= 2.2 mA
V
GS(th)
V
GSq
I
DSS
I
DSX
I
GSS
g
fs
R
DS(on)
gate-source threshold voltage
gate-source quiescent voltage
drain leakage current
drain cut-off current
gate leakage current
forward transconductance
drain-source on-state
resistance
V
DS
= 10 V; I
D
= 220 mA
V
GS
= 0 V; V
DS
= 32 V
V
GS
= V
GS(th)
+ 3.75 V;
V
DS
= 10 V
V
GS
= 11 V; V
DS
= 0 V
V
DS
= 10 V; I
D
= 0.22 A
V
GS
= V
GS(th)
+ 3.75 V;
I
D
= 7.7 A
65
1.5
-
-
-
-
-
-
2.0
-
48
-
2.32
65
-
2.5
2.75
2.8
-
280
-
112
V
V
V
A
A
nA
S
m
V
DS
= 28 V; I
D
= 1000 mA 1.55 2.15
Table 8.
RF characteristics
Specifications are tested with test signal: 1-carrier W-CDMA; PAR = 7.2 dB at 0.01 % probability on
the CCDF; 3GPP test model 1; 1 to 64 DPCH; f
1
= 1805 MHz; f
2
= 1880 MHz; RF performance at
V
DS
= 28 V; I
Dq
= 300 mA (main); V
GS(amp)peak
= 0.5 V; T
case
= 25
C; unless otherwise specified; in
an asymmetrical Doherty production test circuit at frequencies from 1805 MHz to 1880 MHz.
Symbol
G
p
RL
in
D
ACPR
Parameter
power gain
input return loss
drain efficiency
adjacent channel power ratio
Conditions
P
L(AV)
= 47.5 dBm
P
L(AV)
= 47.5 dBm
P
L(AV)
= 47.5 dBm
P
L(AV)
= 47.5 dBm
Min
14.5
-
42.5
-
Typ
15.7
9
47.5
31
Max
-
5
-
26
Unit
dB
dB
%
dBc
BLC9G20LS-361AVT
All information provided in this document is subject to legal disclaimers.
© Ampleon Netherlands B.V. 2017. All rights reserved.
Product data sheet
Rev. 3 — 24 November 2017
3 of 13
BLC9G20LS-361AVT
Power LDMOS transistor
7. Test information
7.1 Ruggedness in Doherty operation
The BLC9G20LS-361AVT is capable of withstanding a load mismatch corresponding to a
VSWR = 10 : 1 through all phases under the following conditions: V
DS
= 28 V;
I
Dq
= 400 mA; V
GS(amp)peak
= 0.5 V; P
L
= 120 W (CW); f = 1805 MHz; tested on the
Doherty development test circuit.
7.2 Impedance information
Table 9.
Typical impedance of main device
Measured load-pull data of main device; I
Dq
= 720 mA; V
DS
= 28 V.
f
(MHz)
1805
1843
1880
1805
1843
1880
[1]
[2]
[3]
Z
S
[1]
()
1.0
j4.0
1.4
j3.9
1.1
j4.1
1.0
j4.0
1.4
j3.9
1.1
j4.1
Z
L
[1]
()
1.4
j3.5
1.4
j3.5
1.4
j3.5
2.8
j2.0
2.6
j1.8
2.4
j2.1
P
L
[2]
(W)
155
151
151
104
102
106
D
[2]
(%)
57.5
57.1
57.1
69.0
69.1
68.3
G
p
[3]
(dB)
18.4
18.0
18.5
20.9
20.5
21.0
Maximum power load
Maximum drain efficiency load
Z
S
and Z
L
defined in
Figure 1.
0.3 dB power back off from 3 dB compression points.
6.0 dB power back off from 3 dB compression points.
Table 10. Typical impedance of peak device
Measured load-pull data of peak device; I
Dq
= 1320 mA; V
DS
= 28 V.
f
(MHz)
1805
1843
1880
1805
1843
1880
[1]
[2]
[3]
Z
S
[1]
()
0.9
j4.8
1.8
j4.9
1.5
j5.4
0.9
j4.8
1.8
j4.9
1.5
j5.4
Z
L
[1]
()
2.3
j3.6
2.3
j3.6
2.3
j3.6
3.4
j1.5
3.1
j1.4
2.7
j1.5
P
L
[2]
(W)
262
256
254
183
176
179
D
[2]
(%)
55.3
54.7
54.6
64.2
63.5
63.1
G
p
[3]
(dB)
19.2
18.7
19.3
21.5
21.1
21.6
Maximum power load
Maximum drain efficiency load
Z
S
and Z
L
defined in
Figure 1.
0.3 dB power back off from 3 dB compression points.
6.0 dB power back off from 3 dB compression points.
BLC9G20LS-361AVT
All information provided in this document is subject to legal disclaimers.
© Ampleon Netherlands B.V. 2017. All rights reserved.
Product data sheet
Rev. 3 — 24 November 2017
4 of 13
BLC9G20LS-361AVT
Power LDMOS transistor
drain
Z
L
gate
Z
S
001aaf059
Fig 1.
Definition of transistor impedance
7.3 Test circuit
50 mm
50 mm
C1 C2
C7
R1
C9
C8
C10
C11
C12
R3
C3
C13
C20
80 mm
C14
C4
C5
C6
R2
C15
C16
C17
C18
C19
aaa-020881
Printed-Circuit Board (PCB): Rogers RO4350B;
r
= 3.5; thickness = 0.508 mm;
thickness copper plating = 35
m.
See
Table 11
for a list of components.
Fig 2.
Component layout for Doherty development test circuit
Table 11. List of components
See
Figure 2
for component layout.
Component
Description
Value
Remarks
Murata
ATC600F
ATC600F
C1, C5, C7, C9, C10, C11, C15, multilayer ceramic chip capacitor 10
F,
50 V
C17, C18
C2, C3, C4, C6, C8, C14, C16
C12, C19
C13
BLC9G20LS-361AVT
multilayer ceramic chip capacitor 9.1 pF
electrolytic capacitor
2200
F,
63 V
multilayer ceramic chip capacitor 8.2 pF
All information provided in this document is subject to legal disclaimers.
© Ampleon Netherlands B.V. 2017. All rights reserved.
Product data sheet
Rev. 3 — 24 November 2017
5 of 13
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