DATASHEET
ISL8023, ISL8024
Compact Synchronous Buck Regulator
The ISL8023, ISL8024 are highly efficient, monolithic,
synchronous step-down DC/DC converters that can deliver 3A
(ISL8023) or 4A (ISL8024) of continuous output current from a
2.7V to 5.5V input supply. The devices use current mode control
architecture to deliver very low duty cycle operation at high
frequency with fast transient response and excellent loop stability.
The ISL8023 and ISL8024 integrate a very low On-resistance
P-Channel (45mΩ) high side FET and N-Channel (19mΩ) low
side FET to maximize efficiency and minimize external
component count. The 100% duty-cycle operation allows less
than 200mV dropout voltage at 4A output current. The
operation frequency of the pulse-width modulator (PWM) is
adjustable from 500kHz to 4MHz. The default switching
frequency of 1MHz is set by connecting the FS pin high, which
allows for the use of small external components.
The ISL8023, ISL8024 can be configured for discontinuous or
forced continuous operation at light load. Forced continuous
operation reduces noise and RF interference while
discontinuous mode provides higher efficiency by reducing
switching losses at light loads.
Fault protection is provided by internal hiccup mode current
limiting during short circuit and overcurrent conditions. Other
protection, such as overvoltage and over-temperature are also
integrated into the device. A power-good output voltage
monitor indicates when the output is in regulation.
The ISL8023, ISL8024 offer a 1ms Power-Good (PG) timer at
power-up. When in shutdown, ISL8023, ISL8024 discharges
the output capacitor through an internal soft-stop switch. Other
features include internal fixed or adjustable soft-start and
internal/external compensation.
The ISL8023 and ISL8024 are offered in a space saving 16 Ld
3x3 Pb-free QFN package with an exposed pad for improved
thermal performance and 1mm maximum height. The
complete converter occupies less than 0.22 in
2
area.
Various fixed output voltages are available upon request. See
the “Ordering Information” on page 4 for more details.
FN7812
Rev 3.00
March 24, 2014
Features
• 2.7V to 5.5V input voltage range
• Very low on-resistance FET’s - P-Channel 45mΩ and
N-Channel 19mΩ typical values
• High efficiency synchronous buck regulator with up to 95%
efficiency
• 0.8% reference accuracy over-temperature/load/line
• Complete BOM with as few as 3 external parts
• Start-up with pre-biased output
• Internal soft-start - 1ms or adjustable
• Soft-stop output discharge during disabled
• Adjustable frequency from 500kHz to 4MHz - default at
1MHz (8023/24), 2MHz (8023A/24A)
• External synchronization up to 4MHz
• Over-temperature, Overcurrent, Overvoltage and negative
overcurrent protection
• Tiny 3x3 QFN package
Applications
• DC/DC POL modules
•
μC/µP,
FPGA and DSP power
• Plug-in DC/DC modules for routers and switchers
• Portable instruments
• Test and measurement systems
• Li-ion battery powered devices
Related Literature
• See
AN1759,
“3A/4A Low Quiescent Current High Efficiency
Synchronous Buck Regulator”
100
90
EFFICIENCY (%)
80
70
60
50
40
0.0 0.5
1.0
1.5 2.0 2.5
I
OUT
(A)
3.0
3.5
4.0
3.3V
OUT
PWM
3.3V
OUT
PFM
FIGURE 1. EFFICIENCY T = +25°C, V
IN
= 5V
FN7812 Rev 3.00
March 24, 2014
Page 1 of 20
ISL8023, ISL8024
Pin Configuration
ISL8023, ISL8024
(16 LD TQFN)
TOP VIEW
PHASE
PHASE
14
PHASE
13
VIN
16
15
VIN 1
VDD 2
PG 3
SYNC 4
12
11
10
9
PGND
PGND
SGND
FB
5
6
7
8
EN
SS
Pin Descriptions
PIN NUMBER
1, 16
2
3
4
SYMBOL
VIN
VDD
PG
SYNC
COMP
FS
DESCRIPTION
Input supply voltage. Connect two 22µF ceramic capacitors to power ground.
Input supply voltage for the logic. Connect VIN PIN.
Power-good is an open-drain output. Use 10kΩ to 100kΩ pull-up resistor connecting between VIN and
PG. At power-up or EN HI, PG rising edge is delayed by 1ms upon output reached within regulation.
Mode Selection pin. Connect to logic high or input voltage VIN for PWM mode. Connect to logic low or
ground for PFM mode. Connect to an external function generator for synchronization with the positive
edge trigger. There is an internal 1MΩ pull-down resistor to prevent an undefined logic state in case
of SYNIN pin float.
Regulator enable pin. Enable the output when driven to high. Shutdown the chip and discharge output
capacitor when driven to low. There is an internal 1MΩ pull-down resistor to prevent an undefined logic
state in case of EN pin float.
This pin sets the oscillator switching frequency, using a resistor, RFS, from the FS pin to GND. The
frequency of operation may be programmed between 500kHz to 4MHz. The default frequency is 1MHz
and configured for internal compensation if FS is connected to VIN.
SS is used to adjust the soft-start time. Set to SGND for internal 1ms rise time. Connect a capacitor from
SS to SGND to adjust the soft-start time. Do not use more than 33nF per IC.
The feedback network of the regulator, VFB, is the negative input to the transconductance error
amplifier. COMP is the output of the amplifier if FS resistor is used. Otherwise COMP is disconnected
thru a MOSFET for internal compensation. Recommend connecting COMP to SGND in internal
compensation mode. The output voltage is set by an external resistor divider connected to VFB. With
a properly selected divider, the output voltage can be set to any voltage between the power rail
(reduced by converter losses) and the 0.6V reference. There is an internal compensation to meet a
typical application. Additional external network across COMP and SGND might be required to improve
the loop compensation of the amplifier operation.
In addition, the regulator power-good and undervoltage protection circuitry use VFB to monitor the
regulator output voltage.
Signal ground.
Power ground.
Switching node connection. Connect to one terminal of the inductor.
The exposed pad must be connected to the SGND pin for proper electrical performance. Place as
much vias as possible under the pad connecting to SGND plane for optimal thermal performance.
5
EN
6
FS
7
8, 9
SS
COMP, FB
10
11, 12
13, 14, 15
Exposed Pad
SGND
PGND
PHASE
-
FN7812 Rev 3.00
March 24, 2014
Page 3 of 20
ISL8023, ISL8024
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
ISL8023IRTAJZ
ISL8024IRTAJZ
ISL8023AIRTAJZ
ISL8024AIRTAJZ
ISL8023EVAL3Z
ISL8024EVAL3Z
ISL8023AEVAL3Z
ISL8024AEVAL3Z
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to
TB347
for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for
ISL8023, ISL8024.
For more information on MSL, please see tech brief
TB363.
023A
024A
23AA
24AA
Evaluation Board
Evaluation Board
Evaluation Board
Evaluation Board
PART
MARKING
OUTPUT VOLTAGE
(V)
Adjustable
Adjustable
Adjustable
Adjustable
TEMP. RANGE
(°C)
-40 to +85
-40 to +85
-40 to +85
-40 to +85
PACKAGE
(Pb-Free)
16 Ld 3x3 TQFN
16 Ld 3x3 TQFN
16 Ld 3x3 TQFN
16 Ld 3x3 TQFN
PKG.
DWG. #
L16.3x3D
L16.3x3D
L16.3x3D
L16.3x3D
Typical Application Diagram
INPUT
2.7V TO 5.5V
VIN
VDD
C1
22µF
EN
R1
100k
PGND
PG
ISL8023, ISL8024
SGND
SYNC
VIN
FS
VFB
COMP
SS
SGND
* C3 is optional. Recommend to
put a placeholder for it. Check
loop analysis first before use.
PHASE
L
1µH
C2
2 x 22µF
R2
200k
R3
100k
C3*
4.7pF
OUTPUT
1.8V/4A
FIGURE 2. TYPICAL APPLICATION DIAGRAM
TABLE 1. COMPONENT SELECTION TABLE
V
OUT
C1
C2
C3
L1
R2
R3
0.8V
22µF
4X22µF
4.7pF
0.47~1µH
33k
100k
1.2V
22µF
2 x 22µF
4.7pF
0.47~1µH
100k
100k
1.5V
22µF
2 x 22µF
4.7pF
0.47~1µH
150k
100k
1.8V
22µF
2 x 22µF
4.7pF
0.68~1.5µH
200k
100k
2.5V
22µF
2 x 22µF
4.7pF
0.68~1.5µH
316k
100k
3.3V
22µF
2 x 22µF
4.7pF
1~2.2µH
450k
100k
3.6
22µF
2 x 22µF
4.7pF
1~2.2µH
500k
100k
FN7812 Rev 3.00
March 24, 2014
Page 4 of 20
Microcontroller MCU
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