HD6473256F datasheet, PDF - EEWORLD Datasheet

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HD6473256F: DescriptionMicrocontroller, 8-Bit, OTPROM, 10MHz, CMOS, PQFP64, QFP-64; CategoryMicrocontrollers and processors; File Size980KB，300 Pages; ManufacturerHitachi （Renesas ）; Websitehttp://www.renesas.com/eng/

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HD6473256F Overview

Microcontroller, 8-Bit, OTPROM, 10MHz, CMOS, PQFP64, QFP-64

HD6473256F Parametric

Parameter Name	Attribute value
Maker	Hitachi （Renesas ）
Parts packaging code	QFP
package instruction	QFP,
Contacts	64
Reach Compliance Code	unknown
Is Samacsys	N
Has ADC	NO
Address bus width	16
bit size	8
maximum clock frequency	10 MHz
DAC channel	NO
DMA channel	NO
External data bus width	8
JESD-30 code	S-PQFP-G64
length	14 mm
Number of I/O lines	53
Number of terminals	64
Maximum operating temperature	75 °C
Minimum operating temperature	-20 °C
PWM channel	NO
Package body material	PLASTIC/EPOXY
encapsulated code	QFP
Package shape	SQUARE
Package form	FLATPACK
Certification status	Not Qualified
ROM programmability	OTPROM
Maximum seat height	3.05 mm
speed	10 MHz
Maximum supply voltage	5.5 V
Minimum supply voltage	4.5 V
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL EXTENDED
Terminal form	GULL WING
Terminal pitch	0.8 mm
Terminal location	QUAD
width	14 mm
uPs/uCs/peripheral integrated circuit type	MICROCONTROLLER
Base Number Matches	1

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Hitachi Single-Chip Microcomputer

H8/325 Series

H8/3257, H8/3256

H8/325, H8/324,

H8/323, H8/322

Hardware Manual

CONTENTS

Section 1. Overview

............................................................................................................... 1

1.1

1.2

1.3

Overview...............................................................................................................................

Block Diagram......................................................................................................................

Pin Assignments and Functions............................................................................................

1.3.1 Pin Arrangement......................................................................................................

1.3.2 Pin Functions ...........................................................................................................

Section 2. MCU Operating Modes and Address Space

................................................ 15

2.1

2.2

2.3

Overview...............................................................................................................................

Mode Descriptions................................................................................................................

Address Space Map ..............................................................................................................

2.3.1 Access Speed ...........................................................................................................

2.3.2 IOS...........................................................................................................................

Mode and System Control Registers (MDCR and SYSCR).................................................

2.4.1 Mode Control Register (MDCR) – H’FFC5 ...........................................................

2.4.2 System Control Register (SYSCR) – H’FFC4 ........................................................

2.4

Section 3. CPU

........................................................................................................................ 27

3.1

3.2

Overview...............................................................................................................................

3.1.1 Features....................................................................................................................

Register Configuration..........................................................................................................

3.2.1 General Registers.....................................................................................................

3.2.2 Control Registers .....................................................................................................

3.2.3 Initial Register Values..............................................................................................

Addressing Modes ................................................................................................................

Data Formats.........................................................................................................................

3.4.1 Data Formats in General Registers..........................................................................

3.4.2 Memory Data Formats.............................................................................................

Instruction Set .......................................................................................................................

3.5.1 Data Transfer Instructions .......................................................................................

3.5.2 Arithmetic Operations .............................................................................................

3.5.3 Logic Operations .....................................................................................................

3.5.4 Shift Operations.......................................................................................................

3.5.5 Bit Manipulations ....................................................................................................

3.5.6 Branching Instructions.............................................................................................

3.5.7 System Control Instructions ....................................................................................

3.3

3.4

3.5

3.6

3.7

3.5.8 Block Data Transfer Instruction ..............................................................................

CPU States ............................................................................................................................

3.6.1 Program Execution State .........................................................................................

3.6.2 Exception-Handling State........................................................................................

3.6.3 Power-Down State ...................................................................................................

Access Timing and Bus Cycle ..............................................................................................

3.7.1 Access to On-Chip Memory (RAM and ROM) ......................................................

3.7.2 Access to On-Chip Register Field and External Devices ........................................

Section 4. Exception Handling

............................................................................................ 61

4.1

4.2

Overview...............................................................................................................................

Reset .....................................................................................................................................

4.2.1 Overview .................................................................................................................

4.2.2 Reset Sequence ........................................................................................................

4.2.3 Disabling of Interrupts after Reset...........................................................................

Interrupts...............................................................................................................................

4.3.1 Overview .................................................................................................................

4.3.2 Interrupt-Related Registers......................................................................................

4.3.3 External Interrupts ...................................................................................................

4.3.4 Internal Interrupts ....................................................................................................

4.3.5 Interrupt Handling ...................................................................................................

4.3.6 Interrupt Response Time..........................................................................................

Note on Stack Handling........................................................................................................

4.3

4.4

Section 5. I/O Ports

................................................................................................................ 77

5.1

5.2

5.3

5.4

5.5

5.6

5.7

5.8

Overview............................................................................................................................... 77

Port 1..................................................................................................................................... 78

Port 2..................................................................................................................................... 81

Port 3..................................................................................................................................... 84

Port 4..................................................................................................................................... 87

Port 5..................................................................................................................................... 94

Port 6..................................................................................................................................... 99

Port 7..................................................................................................................................... 104

Section 6. Parallel Handshaking Interface

....................................................................... 113

6.1

Overview............................................................................................................................... 113

6.1.1 Features.................................................................................................................... 113

6.1.2 Block Diagram......................................................................................................... 114

6.1.3 Input and Output Pins .............................................................................................. 115

6.1.4 Register Configuration ............................................................................................ 115

Register Descriptions............................................................................................................ 115

6.2.1 Port 3 Data Direction Register (P3DDR) ................................................................ 115

6.2.2 Port 3 Data Register (P3DR) ................................................................................... 116

6.2.3 Handshake Control/Status Register (HCSR)........................................................... 116

Operation .............................................................................................................................. 118

6.3.1 Output Timing of Output Strobe Signal .................................................................. 118

6.3.2 Busy Signal Output Timing ..................................................................................... 119

6.3.3 Operation in Software Standby Mode ..................................................................... 119

6.3.4 Sample Application ................................................................................................. 120

6.3.5 Interrupts.................................................................................................................. 121

6.2

6.3

Section 7. 16-Bit Free-Running Timer

.............................................................................. 123

7.1

Overview............................................................................................................................... 123

7.1.1 Features.................................................................................................................... 123

7.1.2 Block Diagram......................................................................................................... 123

7.1.3 Input and Output Pins .............................................................................................. 125

7.1.4 Register Configuration ............................................................................................ 125

Register Descriptions............................................................................................................ 126

7.2.1 Free-Running Counter (FRC) – H’FF92 ................................................................. 126

7.2.2 Output Compare Registers A and B

(OCRA and OCRB) – H’FF94 and H’FF96............................................................ 126

7.2.3 Input Capture Register (ICR) – H’FF98.................................................................. 127

7.2.4 Timer Control Register (TCR) – H’FF90................................................................ 128

7.2.5 Timer Control/Status Register (TCSR) – H’FF91................................................... 130

7.2.6 FRT Noise Canceler Control Register (FNCR) – H’FFFF...................................... 133

CPU Interface ....................................................................................................................... 133

Operation .............................................................................................................................. 136

7.4.1 FRC Incrementation Timing.................................................................................... 136

7.4.2 Output Compare Timing.......................................................................................... 138

7.4.3 FRC Clear Timing ................................................................................................... 138

7.4.4 Input Capture Timing .............................................................................................. 139

7.4.5 Timing of Input Capture Flag (ICF) Setting............................................................ 140

7.2

7.3

7.4

iii

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