Data Sheet
FEATURES
Integrated Optical Module with Ambient
Light Rejection and Two LEDs
ADPD188GG
GENERAL DESCRIPTION
The ADPD188GG is a complete photometric system designed to
measure optical signals from ambient light and from synchronous
reflected light emitting diode (LED) pulses. Synchronous measure-
ment offers best-in-class rejection of ambient light interference,
both dc and ac. The module integrates a highly efficient photo-
metric front end, two LEDs, and two photodiode (PD). All of
these items are housed in a custom package that prevents light
from going directly from the LED to the photodiode without
first entering the subject.
The front end of the application specific integrated circuit (ASIC)
consists of a control block, a 14-bit analog-to-digital converter
(ADC) with a 20-bit burst accumulator, and three flexible,
independently configurable LED drivers. The control circuitry
includes flexible LED signaling and synchronous detection.
The analog front end (AFE) features best-in-class rejection of
signal offset and corruption due to modulated interference
commonly caused by ambient light. The data output and
functional configuration occur over a 1.8 V I
2
C interface or a
serial peripheral interface (SPI) port.
VDD1 VDD2
3.8 mm × 5.0 mm × 0.9 mm module with integrated optical
components
2 green LEDs, 2 PDs with IR cut filter
2 external sensor inputs
3, 370 mA LED drivers
20-bit burst accumulator enabling 20 bits per sample period
On-board sample to sample accumulator enabling up to
27 bits per data read
Custom optical package made to work under a glass window
Optimized SNR for signal limited cases
I
2
C or SPI communications
APPLICATIONS
Optical heart rate monitoring
Reflective SpO
2
measurement
CNIBP measurement
FUNCTIONAL BLOCK DIAGRAM
PDC
ADPD188GG
EXT_IN1
PD1
CH1
TIA_VREF
PD2
EXT_IN2
CH2
PDC
TIA_VREF
PDET1
PD3
CH3
TIA_VREF
PDET2
PD4
CH4
VLED1
GREEN
TIA_VREF
DIGITAL
INTERFACE
AND
CONTROL
BPF
±1 INTEGRATOR
BPF
±1 INTEGRATOR
VREF
1µF
BPF
±1 INTEGRATOR
BPF
CS
±1 INTEGRATOR
TIME SLOT A
DATA
14-BIT
ADC
TIME SLOT B
DATA
SCLK
MOSI
MISO
SDA
SCL
GPIO0
GPIO1
LED1/DNC
LED3
LED2
LED2 DRIVER
LED3 DRIVER
LED1 DRIVER
LGND
NOTES
1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN WHEN USING INTERNAL LEDs.
AGND
DGND
Figure 1.
Rev. A
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16111-001
ADPD188GG
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Analog Specifications ................................................................... 5
Digital Specifications ................................................................... 6
Timing Specifications .................................................................. 7
Absolute Maximum Ratings............................................................ 9
Thermal Resistance ...................................................................... 9
Recommended Soldering Profile ............................................... 9
ESD Caution .................................................................................. 9
Pin Configuration and Function Descriptions ........................... 10
Typical Performance Characteristics ........................................... 11
Theory of Operation ...................................................................... 13
Introduction ................................................................................ 13
Optical Components .................................................................. 13
Dual Time Slot Operation ......................................................... 14
Time Slot Switch ......................................................................... 15
Adjustable Sampling Frequency ............................................... 16
External Synchronization for Sampling .................................. 16
State Machine Operation ........................................................... 16
Normal Mode Operation and Data Flow ................................ 17
Communications Interface ............................................................ 19
I
2
C Interface ................................................................................ 19
SPI Port ........................................................................................ 20
Applications Information .............................................................. 22
Data Sheet
Typical Connection Diagram ................................................... 22
Land Pattern ................................................................................ 22
Recommended Start-Up Sequence .......................................... 23
Reading Data............................................................................... 23
Clocks and Timing Calibration ................................................ 24
Optional Timing Signals Available on GPIO0 and GPIO1 .. 25
LED Driver Pins and LED Supply Voltage.............................. 26
LED Driver Operation ............................................................... 26
Determining the Average Current ........................................... 27
Determining C
VLED
..................................................................... 27
Using External LEDs .................................................................. 28
Calculating Current Consumption .......................................... 28
Mechanical Considerations for Covering the ADPD188GG .... 30
TIA ADC Mode .......................................................................... 30
Pulse Connect Mode .................................................................. 33
Synchronous ECG and PPG Measurement Using TIA ADC
Mode ............................................................................................ 34
Float Mode .................................................................................. 35
Register Listing ............................................................................... 42
LED Control Registers ............................................................... 46
AFE Configuration Registers .................................................... 48
Float Mode Registers ................................................................. 52
System Registers ......................................................................... 54
ADC Registers ............................................................................ 59
Data Registers ............................................................................. 60
Outline Dimensions ....................................................................... 61
Ordering Guide .......................................................................... 61
REVISION HISTORY
10/2018—Rev. 0 to Rev. A
Changes to Figure 24 and Figure 25 ............................................. 22
Changes to Calibrating the 32 kHz Clock Section ..................... 25
Added Improving SNR Using Integrator Chopping Section and
Figure 32; Renumbered Sequentially ........................................... 29
Added Table 18; Renumbered Sequentially ................................ 30
Changes to Table 26 ....................................................................... 42
Changes to Table 29 ....................................................................... 50
Changes to Table 30 ....................................................................... 51
Changes to Address 0x58 Description Column, Table 31 ........ 53
2/2018—Revision 0: Initial Version
Rev. A | Page 2 of 61
Data Sheet
SPECIFICATIONS
ADPD188GG
The voltage applied at the VDD1 and VDD2 pins (V
DD
) = 1.8 V, and T
A
= full operating temperature range, unless otherwise noted.
Table 1.
Parameter
CURRENT CONSUMPTION
Peak V
DD
Supply Current
V
DD
Standby Current
Average V
DD
Supply Current
1 Pulse
Test Conditions/Comments
See the Calculating Current Consumption section for the relevant
equations
Single-channel (Register 0x3C, Bits[8:3] = 0x38)
100 Hz data rate; LED offset = 25 µs; LED pulse period (t
LED_PERIOD
) =
13 µs; LED peak current = 25 mA
Time Slot A only
Time Slot B only
Both Time Slot A and Time Slot B
Time Slot A only
Time Slot B only
Both Time Slot A and Time Slot B
LED peak current = 25 mA
50 Hz data rate
100 Hz data rate
200 Hz data rate
50 Hz data rate
100 Hz data rate
200 Hz data rate
Blackbody color temperature (T = 5500 K)
2
, PDET1 and PDET2
multiplexed into a single channel (1.2 mm
2
active area)
Transimpedance amplifier (TIA) gain = 25 kΩ
TIA gain = 50 kΩ
TIA gain = 100 kΩ
TIA gain = 200 kΩ
Single pulse
64 pulses to 255 pulses
64 pulses to 255 pulses; 128 samples averaged
AFE width = 4 µs
3
AFE width = 3 µs
Time Slot A or Time Slot B; normal mode; 1 pulse;
SLOTA_LED_OFFSET = 23 µs; SLOTA_PERIOD = 19 µs
Both time slots; normal mode; 1 pulse;
SLOTA_LED_OFFSET = 23 µs; SLOTA_PERIOD = 19 µs
Time Slot A or Time Slot B; normal mode; 8 pulses;
SLOTA_LED_OFFSET = 23 µs; SLOTA_PERIOD = 19 µs
Both time slots; normal mode; 8 pulses;
SLOTA_LED_OFFSET = 23 µs; SLOTA_PERIOD = 19 µs
Min
Typ
Max
Unit
4.5
0.3
mA
µA
10 Pulses
53
41
76
107
95
184
3.75
7.5
15
38
75
150
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
Average V
LED
Supply Current
1 Pulse
10 Pulses
SATURATION ILLUMINANCE
1
Direct Illumination
58.8
29.4
14.7
7.4
14
20
27
19
17
2000
1600
1600
1000
kLux
kLux
kLux
kLux
Bits
Bits
Bits
µs
µs
Hz
Hz
Hz
Hz
DATA ACQUISITION
ADC Resolution
Per Sample
Per Data Read
LED PERIOD
Sampling Frequency
4
13
11
0.122
0.122
0.122
0.122
Rev. A | Page 3 of 61
ADPD188GG
Parameter
CATHODE PIN (PDC) VOLTAGE
During All Sampling Periods
During Time Slot A Sampling
Test Conditions/Comments
Register 0x54, Bit 7 = 0x0; Register 0x3C, Bit 9 = 1
5
Register 0x54, Bit 7 = 0x0; Register 0x3C, Bit 9 = 0
Register 0x54, Bit 7 = 0x1; Register 0x54, Bits[9:8] = 0x0
5
Register 0x54, Bit 7 = 0x1; Register 0x54, Bits[9:8] = 0x1
Register 0x54, Bit 7 = 0x1; Register 0x54, Bits[9:8] = 0x2
Register 0x54, Bit 7 = 0x1; Register 0x54, Bits[9:8] = 0x3
6
Register 0x54, Bit 7 = 0x1; Register 0x54, Bits[11:10] = 0x0
5
Register 0x54, Bit 7 = 0x1; Register 0x54, Bits[11:10] = 0x1
Register 0x54, Bit 7 = 0x1; Register 0x54, Bits[11:10] = 0x2
Register 0x54, Bit 7 = 0x1; Register 0x54, Bits[11:10] = 0x3
6
Register 0x54, Bit 7 = 0x0; Register 0x3C, Bit 9 = 1
Register 0x54, Bit 7 = 0x0; Register 0x3C, Bit 9 = 0
Register 0x54, Bit 7 = 0x1; Register 0x54, Bits[13:12] = 0x0
Register 0x54, Bit 7 = 0x1; Register 0x54, Bits[13:12] = 0x1
Register 0x54, Bit 7 = 0x1; Register 0x54, Bits[13:12] = 0x2
Register 0x54, Bit 7 = 0x1; Register 0x54, Bits[13:12] = 0x3
LEDs
LED Peak Current Setting
Dominant Wavelength
7
LED1; Green LED
Luminous Intensity
Photodiode
Responsivity
Active Area
Photodiode 1
Photodiode 2
POWER SUPPLY VOLTAGES
V
DD
V
LED18, 9
DC Power Supply Rejection
Ratio (PSRR)
TEMPERATURE RANGE
Operating
1
Data Sheet
Min
Typ
1.8
1.3
1.8
1.3
TIA_VREF +
0.25
0
1.8
1.3
TIA_VREF +
0.25
0
1.8
1.3
1.8
1.3
TIA_VREF +
0.25
0
12
370
Max
Unit
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
mA
During Time Slot B Sampling
During Sleep Periods
Adjustable via the Register 0x22 through Register 0x25
settings
I
F
= 40 mA
λ = 525 nm, I
F
= 40 mA at 25°C
Wavelength, λ = 525 nm
525
2800
0.25
0.4
0.8
3200
nm
mcd
A/W
mm
2
mm
2
The ADPD188GG does not require a specific power-up sequence
Applied at the VDD1 and VDD2 pins
At 75% full scale input signal
1.7
4
1.8
4.5
24
1.9
5.0
V
V
dB
−40
+85
°C
Saturation illuminance refers to the amount of ambient light that saturates the ADPD188GG signal. Actual results may vary by factors of up to 2× from typical
specifications. As a point of reference, Air Mass 1.5 (AM1.5) sunlight (brightest sunlight) produces 100 kLux.
2
Blackbody color temperature (T = 5800 K) closely matches the light produced by solar radiation (sunlight).
3
Minimum LED period = (2 × AFE width) + 5 µs.
4
The maximum values in this specification are the internal ADC sampling rates in normal mode. The I
2
C read rates in some configurations may limit the output data rate.
5
This mode may induce additional noise and is not recommended unless necessary. The 1.8 V setting uses V
DD
, which contains greater amounts of differential voltage
noise with respect to the anode voltage. A differential voltage between the anode and cathode injects a differential current across the capacitance of the photodiode
of the magnitude of C × dV/dt.
6
This setting is not recommended for photodiodes because it causes a 1.3 V forward bias of the photodiode.
7
I
F
is the forward current of the diode.
8
Set V
LEDx
such that the maximum desired LED current is achievable with the turn on voltage of the LEDs that are wired to the LEDx/DNC pins. The LEDx/DNC pins are
connected to the LEDx driver, which can be modeled as current sinks (see Figure 1). When an appropriate V
LEDx
is used, the voltage at the LEDx/DNC pins adjusts
automatically to accommodate the LED turn on voltage and the LED current.
9
See Figure 9 for the current limitation at the minimum VLED supply voltage, V
LED
.
Rev. A | Page 4 of 61
Data Sheet
ANALOG SPECIFICATIONS
VDD1 = VDD2 = 1.8 V, and T
A
= full operating temperature range, unless otherwise noted.
Table 2.
Parameter
EXT_INx SERIES RESISTANCE (R_IN)
1
PULSED SIGNAL CONVERSIONS, 3 μs
WIDE LED PULSE
2
ADC Resolution
3
Test Conditions/Comments
Measured from −3 µA to +3 µA
4 μs wide AFE integration; normal operation,
Register 0x43 and Register 0x45 = 0xADA5
TIA feedback resistor
25 kΩ
50 kΩ
100 kΩ
200 kΩ
TIA feedback resistor
25 kΩ
50 kΩ
100 kΩ
200 kΩ
TIA feedback resistor
25 kΩ
50 kΩ
100 kΩ
200 kΩ
3 μs wide AFE integration; normal operation, Register 0x43
and Register 0x45 = 0xADA5
TIA feedback resistor
25 kΩ
50 kΩ
100 kΩ
200 kΩ
TIA feedback resistor
25 kΩ
50 kΩ
100 kΩ
200 kΩ
TIA feedback resistor
25 kΩ
50 kΩ
100 kΩ
200 kΩ
FULL SIGNAL CONVERSIONS
4
TIA Saturation Level Pulsed Signal and
Ambient Level
TIA feedback resistor
25 kΩ
50 kΩ
100 kΩ
200 kΩ
TIA feedback resistor
25 kΩ
50 kΩ
100 kΩ
200 kΩ
Rev. A | Page 5 of 61
ADPD188GG
Min
Typ
6.5
Max
Unit
kΩ
3.27
1.64
0.82
0.41
26.8
13.4
6.7
3.35
nA/LSB
nA/LSB
nA/LSB
nA/LSB
μA
μA
μA
μA
ADC Saturation Level
Ambient Signal Headroom on Pulsed
Signal
23.6
11.8
5.9
2.95
μA
μA
μA
μA
PULSED SIGNAL CONVERSIONS, 2 μs
WIDE LED PULSE
2
ADC Resolution
3
4.62
2.31
1.15
0.58
37.84
18.92
9.46
4.73
nA/LSB
nA/LSB
nA/LSB
nA/LSB
μA
μA
μA
μA
ADC Saturation Level
Ambient Signal Headroom on Pulsed
Signal
12.56
6.28
3.14
1.57
μA
μA
μA
μA
50.4
25.2
12.6
6.3
42.8
21.4
10.7
5.4
μA
μA
μA
μA
μA
μA
μA
μA
TIA Linear Range
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