DTS20H23-53PN datasheet, PDF - EEWORLD Datasheet

DTS20H23-53PN: DescriptionHERM RECP; CategoryThe connector; File Size807KB，24 Pages; ManufacturerTE Connectivity; Websitehttp://www.te.com

Download Datasheet Parametric View All

DTS20H23-53PN Online Shopping

Suppliers	Part Number	Price	MOQ	In stock
	DTS20H23-53PN	-	-	View	Buy Now

HERM RECP

Parameter Name	Attribute value
Connector System	line to panel, line to panel
Sealable	yes
Connectors and terminals terminate to	Wires and cables
Housing size	H (23)
Housing type	Square flange female end
Number of Positions	53
Number of power supply locations	0
Number of signal positions	53
Pre-installed	no
Shell material	Stainless steel
Insulation Materials	Glass
Sealed	yes
Contact Current Rating (Max) (A)	7.5
reverse polarity	standard
Terminal layout	23 – 53
Terminal type	Pin
polar code	N
Joint alignment type	keying
Joint fixation type	Thread
Location monitoring	0°
Cable size (AWG)	20 – 24
Working group temperature range	-65 – 200 °C [ -85 – 392 °F ]
Circuit Application	Signal

BRANCHE CONNECTEURS AEROMILITAIRES

DTS series

MIL-DTL-38999 Aluminium

Serie III

[helper2416] The second part of the summary of GDB remote debugging skills of the helper2416 development board: [p=26, null, left][font=宋体][size=3][color=#ff00ff]1. Generate a debuggable program[/color][/size][/font][/p][p=26, null, left][font=宋体][size=3][color=#ff00ff]For example, a source file: main.cpp[/colo...; 陌路绝途 Embedded System

ADF4158 write timing cannot respond: [i=s]This post was last edited by 285062025 on 2014-10-16 15:42[/i] The program for writing the timing of the control lines SPI_CS SPI_CLK SPI_MOSI connected to ADF4158 for debugging ADF5148 is: void ...; 285062025 ADI Reference Circuit

Lwip raw api application problem without operating system: I am currently using FPGA to do network experiments and testing the performance of lwip in raw mode. S3e 500 board, mb core + xilkernel4.0 + lwip130, has been tuned, ping function, tcp and udp data tr...; pocker5200 Embedded System

Quartus adds phase-locked loop problem: There are not three phase-locked loops? The hint is that there are two, and there are only two input clocks, so two phase-locked loops are used, and the other one is not used?...; tianma123 FPGA/CPLD

Shortcut: L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 LA LB LC LD LE LF LG LH LI LJ LK LL LM LN LO LP LQ LR LS LT LU LV LW LX LY LZ M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF MG MH MI MJ MK ML MM MN MO MP MQ MR MS MT MU MV MW MX MY MZ N0 N1 N2 N3 N4 N5 N6 N7 N8 NA NB NC ND NE NF NG NH NI NJ NK NL NM NN NO NP NQ NR NS NT NU NV NX NZ O0 O1 O2 O3 OA OB OC OD OE OF OG OH OI OJ OK OL OM ON OP OQ OR OS OT OV OX OY OZ P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 PA PB PC PD PE PF PG PH PI PJ PK PL PM PN PO PP PQ PR PS PT PU PV PW PX PY PZ Q1 Q2 Q3 Q4 Q5 Q6 Q8 Q9 QA QB QC QE QF QG QH QK QL QM QP QR QS QT QV QW QX QY R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 RA RB RC RD RE RF RG RH RI RJ RK RL RM RN RO RP RQ RR RS RT RU RV RW RX RY RZ

Popular Components