PCA9508
Hot swappable level translating I
2
C-bus repeater
Rev. 01 — 28 April 2008
Product data sheet
1. General description
The PCA9508 is a CMOS integrated circuit that supports hot-swap with zero offset and
provides level shifting between low voltage (down to 0.9 V) and higher voltage (2.7 V to
5.5 V) for I
2
C-bus or SMBus applications. While retaining all the operating modes and
features of the I
2
C-bus system during the level shifts, it also permits extension of the
I
2
C-bus by providing bidirectional buffering for both the data (SDA) and the clock (SCL)
lines, thus enabling two buses of 400 pF. Using the PCA9508 enables the system
designer to isolate two halves of a bus for both voltage and capacitance, and perform
hot-swap and voltage level translation. Furthermore, the dual supply pins can be powered
up in any sequence; when any of the supply pins are unpowered, the 5 V tolerant I/O are
high-impedance.
The hot swap feature allows an I/O card to be inserted into a live backplane without
corrupting the data and clock buses. Control circuitry prevents the backplane from being
connected to the card until a stop command or bus idle occurs on the backplane without
bus contention on the card. Zero offset output voltage allows multiple PCA9508s to be put
in series and still maintains an excellent noise margin.
PCA9508 has B side and A side bus drivers. The 2.7 V to 5.5 V bus B side drivers behave
much like the drivers on the PCA9515A device, while the adjustable voltage bus A side
drivers drive more current and incur no static offset voltage. This results in a LOW on the
B side translating into a nearly 0 V LOW on the A side.
The static offset design of the B side PCA9508 I/O drivers prevents them from being
connected to another device that has a rise time accelerator including the PCA9510/A,
PCA9511/A, PCA9512/A, PCA9513/A, or PCA9514/A or a static offset voltage including
the PCA9507 (B side), PCA9508 (B side), PCA9509 (A side), PCA9515/A, PCA9516A,
PCA9517/A (B side), PCA9518, PCA9519 (A side), or P82B96/PCA9600 (Sx/Sy side).
The A side of two or more PCA9508s can be connected together, however, to allow a star
topology with the A side on the common bus, and the A side can be connected directly to
any other buffer with static or dynamic offset voltage. Multiple PCA9508s can be
connected in series, A side to B side, with no build-up in offset voltage with only
time-of-flight delays to consider.
The PCA9508 drivers are not enabled unless the bus is idle, V
CC(A)
is above 0.8 V and
V
CC(B)
is above 2.5 V. The EN pin can also be used to turn the drivers on and off under
system control. Caution should be observed to only change the state of the enable pin
when the bus is idle.
The output pull-down on the B side internal buffer LOW is set for approximately 0.5 V,
while the input threshold of the internal buffer is set about 70 mV lower (0.43 V). When the
B side I/O is driven LOW internally, the LOW is not recognized as a LOW by the input.
NXP Semiconductors
PCA9508
Hot swappable level translating I
2
C-bus repeater
This prevents a lock-up condition from occurring. The output pull-down on the A side
drives a hard LOW and the input level is set at 0.5V
CC(A)
to accommodate the need for a
lower LOW level in systems where the low voltage side supply voltage is as low as 0.9 V.
Table 1
shows the comparison between PCA9508 and I
2
C-bus repeaters.
Table 1.
Feature
V
CC(A)
range (V)
V
CC(B)
range (V)
rise time
accelerator
idle/stop detect
for hot-swap
normal I/O
static level offset
[1]
PCA9508 and I
2
C-bus repeaters comparison
PCA9507
2.7 to 5.5
2.7 to 5.5
yes
-
A side
B side
PCA9508
0.9 to 5.5
2.7 to 5.5
-
yes
A side
B side
PCA9509
3.0 to 5.5
-
-
B side
A side
PCA9517A
[1]
2.7 to 5.5
-
-
A side
B side
PCA9519
1.1 to V
CC(B)
−
1
3.0 to 5.5
-
-
B side
A side
1.1 to V
CC(B)
−
1 0.9 to 5.5
PCA9517A is the high ESD (6.5 kV HBM and 550 V MM) drop-in replacement for PCA9517.
2. Features
I
2 channel, bidirectional buffer isolates capacitance and allows 400 pF on either side of
the device
I
Supports offset-free hot-swap with IDLE/STOP detect circuitry
I
Voltage level translation from 0.9 V to 5.5 V and from 2.7 V to 5.5 V
I
Footprint and functional replacement for PCA9515, PCA9515A, PCA9517 and
PCA9517A
I
I
2
C-bus and SMBus compatible
I
Active HIGH repeater enable input
I
Static level offset on B side
I
Open-drain input/outputs
I
Lock-up free operation
I
Supports arbitration and clock stretching across the repeater
I
Accommodates Standard-mode and Fast-mode I
2
C-bus devices and multiple masters
I
Powered-off high-impedance I
2
C-bus pins
I
A side operating supply voltage range of 0.9 V to 5.5 V
I
B side operating supply voltage range of 2.7 V to 5.5 V
I
5 V tolerant I
2
C-bus and enable pins
I
0 Hz to 400 kHz clock frequency (the maximum system operating frequency may be
less than 400 kHz because of the delays added by the repeater).
I
ESD protection exceeds 6000 V HBM per JESD22-A114, 450 V MM per
JESD22-A115, and 1000 V CDM per JESD22-C101
I
Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
I
Packages offered: SO8 and TSSOP8
PCA9508_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 28 April 2008
2 of 21
NXP Semiconductors
PCA9508
Hot swappable level translating I
2
C-bus repeater
3. Ordering information
Table 2.
Ordering information
T
amb
=
−
40
°
C to +85
°
C.
Type number
PCA9508D
PCA9508DP
[1]
Topside
mark
Package
Name
Description
plastic small outline package; 8 leads; body width 3.9 mm
Version
SOT96-1
SOT505-1
PCA9508 SO8
9508
TSSOP8
[1]
plastic thin shrink small outline package; 8 leads; body width 3 mm
Also known as MSOP8.
4. Functional diagram
V
CC(A)
V
CC(B)
PCA9508
SDAA
SDAB
SCLA
SCLB
CONNECT
0.55V
CC
/
0.45V
CC
STOP BIT AND
BUS IDLE
V
CC(B)
pull-up
resistor
0.5
µA
0.55V
CC
/
0.45V
CC
UVLO
EN
100
µs
DELAY
20 pF
UVLO
RD
S
QB
CONNECT
0.5 pF
002aac651
Fig 1.
Functional diagram of PCA9508
PCA9508_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 28 April 2008
3 of 21
NXP Semiconductors
PCA9508
Hot swappable level translating I
2
C-bus repeater
5. Pinning information
5.1 Pinning
V
CC(A)
SCLA
SDAA
GND
1
2
8
7
V
CC(B)
SCLB
SDAB
EN
V
CC(A)
SCLA
SDAA
GND
1
2
3
4
002aac653
8
7
V
CC(B)
SCLB
SDAB
EN
PCA9508D
3
4
002aac652
6
5
PCA9508DP
6
5
Fig 2.
Pin configuration for SO8
Fig 3.
Pin configuration for TSSOP8
5.2 Pin description
Table 3.
Symbol
V
CC(A)
SCLA
SDAA
GND
EN
SDAB
SCLB
V
CC(B)
Pin description
Pin
1
2
3
4
5
6
7
8
Description
A side supply voltage (0.9 V to 5.5 V)
open-drain input/output serial clock A side bus
open-drain input/output serial data A side bus
supply ground (0 V)
active HIGH repeater enable input with an internal pull-up (100 kΩ)
open-drain input/output serial data B side bus
open-drain input/output serial clock B side bus
B side supply voltage (2.7 V to 5.5 V)
6. Functional description
Refer to
Figure 1 “Functional diagram of PCA9508”.
The PCA9508 enables I
2
C-bus or SMBus translation down to V
CC(A)
as low as 0.9 V
without degradation of system performance. The PCA9508 contains two bidirectional
open-drain buffers specifically designed to provide superior hot-swap and/or support
up-translation/down-translation between the low voltage (as low as 0.9 V) and a 3.3 V or
5 V I
2
C-bus or SMBus. All inputs and I/Os are overvoltage tolerant to 5.5 V even when the
device is unpowered (V
CC(B)
and/or V
CC(A)
= 0 V). The PCA9508 includes a power-up
circuit that keeps the output drivers turned off until V
CC(B)
is above 2.5 V and the V
CC(A)
is
above 0.8 V. V
CC(B)
and V
CC(A)
can be applied in any sequence at power-up. V
CC(A)
is only
used to provide the 0.5V
CC(A)
reference to the A side input comparators and for the power
good detect circuit. The PCA9508 logic and all I/Os are powered by the V
CC(B)
pin.
An undervoltage/initialization circuit holds the PCA9508 in a disconnected state which
presents high-impedance to all SDA and SCL pins during power-up. A LOW on the enable
pin (EN) also forces the parts into the disconnected state. As the power supply is brought
up and EN is HIGH or the part is powered and EN is taken from LOW to HIGH it enters an
initialization state where the internal references are stabilized. At the end of the
initialization state the ‘STOP bit and bus idle’ detect circuit is enabled. With the EN pin
PCA9508_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 28 April 2008
4 of 21
NXP Semiconductors
PCA9508
Hot swappable level translating I
2
C-bus repeater
HIGH long enough to complete the initialization state (t
en
) and remaining HIGH when all
the SDA and SCL pins have been HIGH for the bus idle time or when all pins are HIGH
and a STOP condition is seen on the SDAA and SCLA pins, SDAA is connected to SDAB
and SCLA is connected to SCLB.
6.1 A side to B side
Once connected, when the PCA9508 senses a LOW level on the A side (below
0.5V
CC(A)
), it turns on the corresponding B side driver (either SDA or SCL) and drives the
B side down to about 0.5 V. When the external driver turns off, the A side will begin to rise
as it is pulled HIGH by the bus pull-up resistor. When the A side reaches 0.5V
CC(A)
, the
B side driver turns off and both A and B will continue to rise. The result is two smooth
exponential rising edges on both buses with a propagation delay between them which is a
function of the RC time constant on the A side bus.
6.2 B side to A side
When a LOW level is sensed on the B side (below 0.4 V), the corresponding A side driver
is turned on to drive the A side to nearly 0 V. When the external driver turns off, the B side
will begin to rise as it is pulled HIGH by the bus pull-up resistor. When the B side reaches
0.5 V, the A side driver will turn off. The B side driver will remain at about 0.5 V until the
A side rises above 0.5V
CC(A)
, then the B side will continue to rise. The result is a plateau
on the B side rising edge. See
Figure 11.
6.3 Weak drive on B side
The following condition should be avoided as it causes the PCA9508 to create a glitch on
the bus. As long as I
2
C-bus devices connected to the B side can pull the bus lines lower
than 0.4 V, this problem will never occur. When the B side falls first and goes below
0.3V
CC(B)
, the A side driver is turned on and the A side is pulled down to 0 V. The B side
pull-down is switched on and unless the B side is pulled below 0.4 V by an external driver,
the A side pull-down will switch off and the A side will be pulled up by the pull-up resistor.
When the A side rises above 0.5V
CC(A)
, the B side pull-down will turn off. To prevent this
glitch, it is necessary to make certain that the B side LOW level driven by an external
driver is below 0.4 V.
6.4 Enable pin (EN)
The EN pin is active HIGH with an internal pull-up to V
CC(B)
and allows the user to select
when the repeater is active. This can be used to isolate a badly behaved slave on
power-up until after the system power-up reset. It should never change state during an
I
2
C-bus operation because disabling during a bus operation will hang the bus.
The EN pin should only change state when the global bus and the repeater port are in an
idle state to prevent system failures.
If the PCA9508 is enabled while the bus is active, the PCA9508 will connect at the first
STOP signal or at the first gap in activity that satisfies the internal idle bus time after the
enable sequence is complete.
PCA9508_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 28 April 2008
5 of 21
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