PL123-09NSI-R datasheet, PDF - EEWORLD Datasheet

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PL123-09NSI-R: DescriptionIC CLK BUFFER 1:9 134MHZ 16SOIC; Categorylogic logic; File Size343KB，9 Pages; ManufacturerMicrochip; Websitehttps://www.microchip.com; Environmental Compliance

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PL123-09NSI-R Overview

IC CLK BUFFER 1:9 134MHZ 16SOIC

PL123-09NSI-R Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Microchip
package instruction	SOP,
Reach Compliance Code	compliant
Factory Lead Time	6 weeks
series	PL123
Input adjustment	STANDARD
JESD-30 code	R-PDSO-G16
JESD-609 code	e3
length	9.9 mm
Logic integrated circuit type	PLL BASED CLOCK DRIVER
Humidity sensitivity level	1
Number of functions	1
Number of inverted outputs
Number of terminals	16
Actual output times	9
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Peak Reflow Temperature (Celsius)	260
propagation delay (tpd)	9.2 ns
Same Edge Skew-Max（tskwd）	0.25 ns
Maximum seat height	1.75 mm
Maximum supply voltage (Vsup)	3.63 V
Minimum supply voltage (Vsup)	1.62 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
Temperature level	INDUSTRIAL
Terminal surface	Matte Tin (Sn) - annealed
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	40
width	3.9 mm

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PL123-05/-09

Low Skew Zero Delay Buffer

FEATURES



Frequency Range 10MHz to 134 MHz

Output Options:

5 outputs

PL123-05

9 outputs

PL123-09

Zero input - output delay

Optional Drive Strength:

Standard (8mA)

PL123-05/-09

High (12mA)

PL123-05H/-09H

3.3V, ±10% operation

Available in Commercial and Industrial temperature

ranges

Available in 16-Pin SOP or TSSOP (PL123-09),

and 8-Pin SOP (PL123-05) packages

DESCRIPTION

The PL123-05/-09 (-05H/-09H for High Drive) are high

performance, low skew, low jitter zero delay buffers

designed to distribute high speed clocks. They have

one (PL123-05) or two (PL123-09) low-skew output

banks, of 4 outputs each, that are synchronized with

the input. The PL123-09 allows control of the banks of

outputs by using the S1 and S2 inputs as shown in the

Selector Definition table on page 2.

The synchronization is established via CLKOUT feed

back to the input of the PLL. Since the skew between

the input and output is less than

100ps,

the device

acts as a zero delay buffer. The input output propaga-

tion delay can be advanced or delayed by adjusting the

load on the CLKOUT pin.

These parts are not intended for 5V input-tolerant ap-

plications.

BLOCK DIAGRAM

REF

PLL

Mux

CLKOUT

CLKA1

REF

CLKA2

CLKA1

CLKOUT

CLKA4

VDD

CLKA3

PL123-05

Bank A

CLKA2

CLKA3

CLKA4

CLKB1

GND

REF

CLKA1

CLKA2

VDD

CLKOUT

CLKA4

CLKA3

VDD

GND

CLKB4

CLKB3

PL123-09

Bank B

Selector

Inputs

(PL123-09 Only)

CLKB2

CLKB3

CLKB4

GND

CLKB1

CLKB2

Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 •

www.micrel.com

Rev 4/22/13

Page 1

PL123-09NSI-R Related Products

	PL123-09NSI-R	PL123-05NSC-R	PL123-09NSC	PL123-05NSI	PL123-09HOC	PL123-09NSC-R	PL123-09NOC-R	PL123-09NOC	PL123-09SC-R	PL123-05HSC-R
Description	IC CLK BUFFER 1:9 134MHZ 16SOIC	clock buffer DC - 134mhz 1:5 fanout buffer	clock buffer DC - 134mhz 1:9 fanout buffer	clock buffer DC - 134mhz 1:5 fanout buffer	clock buffer low skew 1:9 zero delay buffer	clock buffer DC - 134mhz 1:9 fanout buffer	clock buffer low skew 1:9 zero delay buffer	clock buffer low skew 1:9 zero delay buffer	clock buffer low skew 1:9 zero delay buffer	clock buffer low skew 1:5 zero delay buffer
Is it Rohs certified?	conform to	conform to	conform to	conform to	-	conform to	-	-	conform to	conform to
Maker	Microchip	Microchip	Microchip	Microchip	Microchip	Microchip	-	-	Microchip	Microchip
package instruction	SOP,	GREEN, SOP-8	SOP,	GREEN, SOP-8	GREEN, TSSOP-16	SOP,	-	-	SOP,	GREEN, SOP-8
Reach Compliance Code	compliant	compli	compli	compli	compli	compli	-	-	compli	compli
Factory Lead Time	6 weeks	6 weeks	6 weeks	6 weeks	-	6 weeks	-	-	6 weeks	6 weeks
series	PL123	PL123	PL123	PL123	PL123	PL123	-	-	PL123	PL123
Input adjustment	STANDARD	STANDARD	STANDARD	STANDARD	MUX	STANDARD	-	-	MUX	MUX
JESD-30 code	R-PDSO-G16	R-PDSO-G8	R-PDSO-G16	R-PDSO-G8	R-PDSO-G16	R-PDSO-G16	-	-	R-PDSO-G16	R-PDSO-G8
JESD-609 code	e3	e3	e3	e3	-	e3	-	-	e3	e3
length	9.9 mm	4.9 mm	9.9 mm	4.9 mm	5 mm	9.9 mm	-	-	9.9 mm	4.9 mm
Logic integrated circuit type	PLL BASED CLOCK DRIVER	PLL BASED CLOCK DRIVER	PLL BASED CLOCK DRIVER	PLL BASED CLOCK DRIVER	PLL BASED CLOCK DRIVER	PLL BASED CLOCK DRIVER	-	-	PLL BASED CLOCK DRIVER	PLL BASED CLOCK DRIVER
Humidity sensitivity level	1	3	1	3	-	1	-	-	-	3
Number of functions	1	1	1	1	1	1	-	-	1	1
Number of terminals	16	8	16	8	16	16	-	-	16	8
Actual output times	9	5	9	5	9	9	-	-	9	5
Maximum operating temperature	85 °C	70 °C	70 °C	85 °C	70 °C	70 °C	-	-	70 °C	70 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	-	-	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	SOP	SOP	SOP	SOP	TSSOP	SOP	-	-	SOP	SOP
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	-	-	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE	SMALL OUTLINE	SMALL OUTLINE	SMALL OUTLINE	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE	-	-	SMALL OUTLINE	SMALL OUTLINE
Peak Reflow Temperature (Celsius)	260	260	260	260	-	260	-	-	-	260
propagation delay (tpd)	9.2 ns	9.2 ns	9.2 ns	9.2 ns	8.5 ns	9.2 ns	-	-	8.5 ns	0.35 ns
Same Edge Skew-Max（tskwd）	0.25 ns	0.25 ns	0.25 ns	0.25 ns	0.25 ns	0.25 ns	-	-	0.25 ns	0.25 ns
Maximum seat height	1.75 mm	1.75 mm	1.75 mm	1.75 mm	1.2 mm	1.75 mm	-	-	1.75 mm	1.75 mm
Maximum supply voltage (Vsup)	3.63 V	3.63 V	3.63 V	3.63 V	3.6 V	3.63 V	-	-	3.6 V	3.6 V
Minimum supply voltage (Vsup)	1.62 V	1.62 V	1.62 V	1.62 V	3 V	1.62 V	-	-	3 V	3 V
Nominal supply voltage (Vsup)	1.8 V	1.8 V	1.8 V	1.8 V	3.3 V	1.8 V	-	-	3.3 V	3.3 V
surface mount	YES	YES	YES	YES	YES	YES	-	-	YES	YES
Temperature level	INDUSTRIAL	COMMERCIAL	COMMERCIAL	INDUSTRIAL	COMMERCIAL	COMMERCIAL	-	-	COMMERCIAL	COMMERCIAL
Terminal surface	Matte Tin (Sn) - annealed	Matte Tin (Sn) - annealed	Matte Tin (Sn) - annealed	Matte Tin (Sn) - annealed	-	Matte Tin (Sn) - annealed	-	-	Matte Tin (Sn) - annealed	Matte Tin (Sn) - annealed
Terminal form	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	-	-	GULL WING	GULL WING
Terminal pitch	1.27 mm	1.27 mm	1.27 mm	1.27 mm	0.65 mm	1.27 mm	-	-	1.27 mm	1.27 mm
Terminal location	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	-	-	DUAL	DUAL
Maximum time at peak reflow temperature	40	40	40	40	-	40	-	-	-	40
width	3.9 mm	3.9 mm	3.9 mm	3.9 mm	4.4 mm	3.9 mm	-	-	3.9 mm	3.9 mm

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