InnoSwitch3-EP
Family
Off-Line CV/CC QR Flyback Switcher IC with Integrated
725 V MOSFET, Synchronous Rectification and FluxLink Feedback.
For Applications up to 45 W
Product Highlights
Highly Integrated, Compact Footprint
•
Up to 94% efficiency across full load range
•
Incorporates a multi-mode Quasi-Resonant (QR) / CCM flyback
SR FET
•
•
•
•
controller, 725 V MOSFET, secondary-side sensing and synchronous
rectification driver
Excellent multi-output cross regulation with weighted secondary-side
regulation (SSR) feedback and synch FETs
Integrated FluxLink™, HIPOT-isolated, feedback link
Exceptional CV/CC accuracy, independent of external components
Adjustable accurate output current sense using external output sense
resistor
FWD
GND
BPS
SR
InnoSwitch3-EP
Primary FET
and Controller
D
V
FB
VOUT
Optional
Current
Sense
EcoSmart™ – Energy Efficient
S
BPP
IS
•
Less than 15 mW no-load including line sense
•
Easily meets all global energy efficiency regulations
•
Low heat dissipation
Secondary
Control IC
PI-8184-050217
Advanced Protection / Safety Features
•
•
•
•
Figure 1.
Typical Application Schematic.
Secondary MOSFET or diode short-circuit protection
Open SR FET-gate detection
Fast input line UV/OV protection
Auto-restart fault response for output OVP
Optional Features
•
Auto-restart output UV protection with option for peak power delivery
Full Safety and Regulatory Compliance
•
•
•
•
•
Reinforced isolation
Isolation voltage >4000 VAC
100% production HIPOT testing
UL1577 and TUV (EN60950) safety approved
Excellent noise immunity enables designs that achieve class “A”
performance criteria for EN61000-4 suite; EN61000-4-2, 4-3
(30 V/m), 4-4, 4-5, 4-6, 4-8 (100 A/m) and 4-9 (1000 A/m)
Figure 2.
High Creepage, Safety-Compliant InSOP-24D Package.
Output Power Table
230 VAC ± 15%
Product
INN3672C
INN3673C
INN3674C
INN3675C
INN3676C
INN3677C
3
85-265 VAC
Peak or
Open Frame
1,2
10 W
12 W
20 W
25 W
36 W
40 W
Green Package
Applications
Peak or
Open Frame
1,2
12 W
15 W
25 W
30 W
40 W
45 W
•
Halogen free and RoHS compliant
•
Auxiliary, standby and bias power supplies for appliances, computers
•
Utility meter, smart grid and industrial power supplies
and consumer products
Description
The InnoSwitch™3-EP family of ICs dramatically simplifies the design
and manufacture of flyback power converters, particularly those
requiring high efficiency and/or compact size. The InnoSwitch3-EP
family combines primary and secondary controllers and safety-rated
feedback into a single IC.
InnoSwitch3-EP family devices incorporate multiple protection features
including line over and undervoltage protection, output overvoltage
and over-current limiting, and over-temperature shutdown. Devices are
available with standard and peak power delivery options, and
commonly used auto-restart protection behaviors.
Table 1. Output Power Table.
Notes:
1. Minimum continuous power in a typical non-ventilated enclosed typical size
adapter measured at 40 °C ambient. Max output power is dependent on the
design. With condition that package temperature must be < 125 °C.
2. Minimum peak power capability.
3. Package: InSOP-24D.
www.power.com
August 2018
This Product is Covered by Patents and/or Pending Patent Applications.
InnoSwitch3-EP
DRAIN
(D)
UNDER/OVER
INPUT VOLTAGE (V)
PRIMARY BYPASS
REGULATOR
ENABLE
ENABLE
LINE
INTERFACE
BPP/UV
UV/OV
GATE
OSCILLATOR/
TIMERS
JITTER
AUTO-RESTART
COUNTER
RESET
PRIMARY BYPASS
(BPP)
FAULT
BPP/UV
PRIMARY
BYPASS PIN
UNDERVOLTAGE
+
-
GATE
PRIM-CLK
PRIMARY
BYPASS PIN
CAPACITOR
SELECT AND
CURRENT
LIMIT
V
ILIM
V
SHUNT
V
BP+
t
ON(MAX)
THERMAL
SHUTDOWN
GATE
SenseFET
BPP
t
OFF(BLOCK)
GATE
OV/UV
LATCH-OFF
Q
S
R
FAULT
SecREQ
PRIM/SEC
SecPulse
PRIM/SEC
Power
MOSFET
From
Secondary
Controller
RECEIVER
CONTROLLER
DRIVER
I
S
LEB
BPP/UV
ILIM
Q
SEC-
LATCH
t
OFF(BLOCK)
PRIM-CLK
+
V
ILIM
-
LATCH-OFF
t
ON(MAX)
PRIMARY OVP
LATCH
PI-8044-083017
SOURCE
(S)
Figure 3.
Primary Controller Block Diagram.
FORWARD
(FWD)
SYNCRONOUS RECTIFIER DRIVE
(SR)
OUTPUT VOLTAGE
(VOUT)
SR CONTROL
REGULATOR
4.4 V
SECONDARY
BYPASS
(BPS)
INH
VOUT
FORWARD
ENABLE
SR
BPS
UV
+
-
DETECTOR
+
S
R
Q
Q
4.4 V
3.9 V
SR
THRESHOLD
QR
HANDSHAKE/
LATCH-OFF
CONTROL
INH
DCM
SECONDARY
LATCH
FEEDBACK
(FB)
VREF
To
Primary
Receiver
FEEDBACK
DRIVER
INH
QR
+
-
FEEDBACK
COMPENSATION
Ts
MAX
t
OFF(MIN)
OSCILLATOR/
TIMER
t
SS(RAMP)
V
PK
t
SECINH(MAX)
+
-
CONSTANT
POWER
IS THRESHOLD
SECONDARY
GROUND
(GND)
ISENSE
(IS)
PI-8045d-091217
Figure 4.
Secondary Controller Block Diagram.
2
Rev. D 08/18
www.power.com
InnoSwitch3-EP
Pin Functional Description
ISENSE (IS) Pin (Pin 1)
Connection to the power supply output terminals. An external
current sense resistor should be connected between this and the
GND pin. If current regulation is not required, this pin should be tied
to the GND pin.
SECONDARY GROUND (GND) (Pin 2)
GND for the secondary IC. Note this is not the power supply output
GND due to the presence of the sense resistor between this and the
ISENSE pin.
FEEDBACK (FB) Pin (Pin 3)
Connection to an external resistor divider to set the power supply
output voltage.
SECONDARY BYPASS (BPS) Pin (Pin 4)
Connection point for an external bypass capacitor for the secondary
IC supply.
SYNCHRONOUS RECTIFIER DRIVE (SR) Pin (Pin 5)
Gate driver for external SR FET. If no SR FET is used connect this pin
to GND.
OUTPUT VOLTAGE (VOUT) Pin (Pin 6)
Connected directly to the output voltage, to provide current for the
controller on the secondary-side and provide secondary protection.
FORWARD (FWD) Pin (Pin 7)
The connection point to the switching node of the transformer output
winding providing information on primary switch timing. Provides power
for the secondary-side controller when V
OUT
is below threshold.
NC Pin (Pin 8-12)
Leave open. Should not be connected to any other pins.
UNDER/OVER INPUT VOLTAGE (V) Pin (Pin 13)
A high-voltage pin connected to the AC or DC side of the input bridge
for detecting undervoltage and overvoltage conditions at the power
supply input. This pin should be tied to SOURCE pin to disable UV/OV
protection.
PRIMARY BYPASS (BPP) Pin (Pin 14)
The connection point for an external bypass capacitor for the
primary-side supply. This is also the ILIM selection pin for choosing
standard ILIM or ILIM+1.
NC Pin (Pin 15)
Leave open. Should not be connected to any other pins.
SOURCE (S) Pin (Pin 16-19)
These pins are the power MOSFET source connection. Also ground
reference for primary BYPASS pin.
DRAIN (D) Pin (Pin 24)
Power MOSFET drain connection.
Figure 5.
Pin Configuration.
V 13
BPP 14
NC 15
S 16-19
D 24
12 NC
11 NC
10 NC
9 NC
8 NC
7 FWD
6 VOUT
5 SR
4 BPS
3 FB
2 GND
1 IS
PI-7877-022216
InnoSwitch3-EP Functional Description
The InnoSwitch3-EP combines a high-voltage power MOSFET switch,
along with both primary-side and secondary-side controllers in one
device.
The architecture incorporates a novel inductive coupling feedback
scheme (FluxLink) using the package lead frame and bond wires to
provide a safe, reliable, and cost-effective means to transmit
accurate, output voltage and current information from the secondary
controller to the primary controller.
The primary controller on InnoSwitch3-EP is a Quasi-Resonant (QR)
flyback controller that has the ability to operate in continuous
conduction mode (CCM), boundary mode (CrM) and discontinuous
conduction mode (DCM). The controller uses both variable frequency
and variable current control schemes. The primary controller consists
of a frequency jitter oscillator, a receiver circuit magnetically coupled to
the secondary controller, a current limit controller, 5 V regulator on
the PRIMARY BYPASS pin, audible noise reduction engine for light
load operation, bypass overvoltage detection circuit, a lossless input
line sensing circuit, current limit selection circuitry, over-temperature
protection, leading edge blanking, secondary output diode / SR FET
short protection circuit and a 725 V power MOSFET.
The InnoSwitch3-EP secondary controller consists of a transmitter
circuit that is magnetically coupled to the primary receiver, a constant
voltage (CV) and a constant current (CC) control circuit, a 4.4 V
regulator on the SECONDARY BYPASS pin, synchronous rectifier FET
driver, QR mode circuit, oscillator and timing circuit, and numerous
integrated protection features.
Figure 3 and Figure 4 show the functional block diagrams of the
primary and secondary controller, highlighting the most important
features.
3
www.power.com
Rev. D 08/18
InnoSwitch3-EP
PI-8205-120516
Primary Controller
Normalized I
LIM
(A)
InnoSwitch3-EP has variable frequency QR controller plus CCM/CrM/
DCM operation for enhanced efficiency and extended output power
capability.
PRIMARY BYPASS Pin Regulator
The PRIMARY BYPASS pin has an internal regulator that charges the
PRIMARY BYPASS pin capacitor to V
BPP
by drawing current from the
DRAIN pin whenever the power MOSFET is off. The PRIMARY
BYPASS pin is the internal supply voltage node. When the power
MOSFET is on, the device operates from the energy stored in the
PRIMARY BYPASS pin capacitor.
In addition, a shunt regulator clamps the PRIMARY BYPASS pin
voltage to V
SHUNT
when current is provided to the PRIMARY BYPASS
pin through an external resistor. This allows the InnoSwitch3-EP to
be powered externally through a bias winding, decreasing the no-load
consumption to less than 15 mW in a 5 V output design.
Primary Bypass ILIM Programming
InnoSwitch3-EP ICs allows the user to adjust current limit (ILIM)
settings through the selection of the PRIMARY BYPASS pin capacitor
value. A ceramic capacitor can be used.
There are 2 selectable capacitor sizes - 0.47
mF
and 4.7
mF
for setting
standard and increased ILIM settings respectively.
Primary Bypass Undervoltage Threshold
The PRIMARY BYPASS pin undervoltage circuitry disables the power
MOSFET when the PRIMARY BYPASS pin voltage drops below ~4.5 V
(V
BPP
- V
BP(H)
) in steady-state operation. Once the PRIMARY BYPASS
pin voltage falls below this threshold, it must rise to V
SHUNT
to
re-enable turn-on of the power MOSFET.
Primary Bypass Output Overvoltage Function
The PRIMARY BYPASS pin has a latching OV protection feature. A
Zener diode in parallel with the resistor in series with the PRIMARY
BYPASS pin capacitor is typically used to detect an overvoltage on the
primary bias winding and activate the protection mechanism. In the
event that the current into the PRIMARY BYPASS pin exceeds ISD, the
device will latch-off or disable the power MOSFET switching for a time
t
AR(OFF)
, after which time the controller will restart and attempt to
return to regulation (see Secondary Fault Response in the Feature
Code Addenda).
VOUT OV protection is also included as an integrated feature on the
secondary controller (see Output Voltage Protection).
Over-Temperature Protection
The thermal shutdown circuitry senses the primary MOSFET die
temperature. The threshold is set to T
SD
with either a hysteretic or
latch-off response.
Hysteretic response: If the die temperature rises above the threshold,
the power MOSFET is disabled and remains disabled until the die
temperature falls by T
SD(H)
at which point switching is re-enabled. A
large amount of hysteresis is provided to prevent over-heating of the
PCB due to a continuous fault condition.
Latch-off response: If the die temperature rises above the threshold
the power MOSFET is disabled. The latching condition is reset by
bringing the PRIMARY BYPASS pin below V
BPP(RESET)
or by going below
the UNDER/OVER INPUT VOLTAGE pin UV (I
UV-
) threshold.
1.05
1.0
0.95
0.9
0.85
0.8
0.75
30
40
50
60
70
80
90
100
Steady-State Switching Frequency (kHz)
Figure 6.
Normalized Primary Current vs. Frequency.
Current Limit Operation
The primary-side controller has a current limit threshold ramp that is
linearly decreasing to the time from the end of the previous primary
switching cycle (i.e. from the time the primary MOSFET turns off at
the end of a switching cycle).
This characteristic produces a primary current limit that increases as
the switching frequency (load) increases (Figure 6).
This algorithm enables the most efficient use of the primary switch
with the benefit that this algorithm responds to digital feedback
information immediately when a feedback switching cycle request is
received.
At high load, switching cycles have a maximum current approaching
100% I
LIM
. This gradually reduces to 30% of the full current limit as
load decreases. Once 30% current limit is reached, there is no
further reduction in current limit (since this is low enough to avoid
audible noise). The time between switching cycles will continue to
increase as load reduces.
Jitter
The normalized current limit is modulated between 100% and 95%
at a modulation frequency of f
M
. This results in a frequency jitter of
~7 kHz with average frequency of ~100 kHz.
Auto-Restart
In the event a fault condition occurs (such as an output overload,
output short-circuit, or external component/pin fault), the
InnoSwitch3-EP enters auto-restart (AR) or latches off. The latching
condition is reset by bringing the PRIMARY BYPASS pin below ~3 V or
by going below the UNDER/OVER INPUT VOLTAGE pin UV (I
UV-
)
threshold.
In auto-restart, switching of the power MOSFET is disabled for t
AR(OFF)
.
There are 2 ways to enter auto-restart:
1.
Continuous secondary requests at above the overload detection
frequency f
OVL
(~110 kHz) for longer than 82 ms (t
AR
).
2.
No requests for switching cycles from the secondary for >t
AR(SK)
.
The second is included to ensure that if communication is lost, the
primary tries to restart. Although this should never be the case in
normal operation, it can be useful when system ESD events (for
example) causes a loss of communication due to noise disturbing the
secondary controller. The issue is resolved when the primary restarts
after an auto-restart off-time.
4
Rev. D 08/18
www.power.com
InnoSwitch3-EP
The first auto-restart off-time is short (t
AR(OFF)SH
). This short auto-
restart time is to provide quick recovery under fast reset conditions.
The short auto-restart off-time allows the controller to quickly check to
determine whether the auto-restart condition is maintained beyond
t
AR(OFF)SH
. If so, it will resort to a full auto-restart off-time.
The auto-restart is reset as soon as an AC reset occurs.
SOA Protection
In the event that there are two consecutive cycles where the I
LIM
is
reached within ~500 ns (the blanking time + current limit delay time),
the controller will skip 2.5 cycles or ~25
ms
(based on full frequency
of 100 kHz). This provides sufficient time for the transformer to reset
with large capacitive loads without extending the start-up time.
Secondary Rectifier/SR MOSFET Short Protection (SRS)
In the event that the output diode or SR FET is short-circuited before
or during the primary conduction cycle, the drain current (prior to the
end of the leading edge blanking time) can be much higher than the
maximum current limit threshold. If the controller turns the high-
voltage power MOSFET off, the resulting peak drain voltage could
exceed the rated BV
DSS
of the device, resulting in catastrophic failure
even with minimum on-time.
To address this issue, the controller features a circuit that reacts
when the drain current exceeds the maximum current limit threshold
prior to the end of leading-edge blanking time. If the leading-edge
current exceeds current limit within a cycle (200 ns), the primary
controller will trigger a 30
ms
off-time event. SOA mode is triggered if
there are two consecutive cycles above current limit within t
LES
(~500 ns). SRS mode also triggers ~200 ms off-time, if the current
limit is reached within 200 ns after a 30
ms
off-time.
Input Line Voltage Monitoring
The UNDER/OVER INPUT VOLTAGE pin is used for input undervoltage
and overvoltage sensing and protection.
A 4 MΩ resistor is tied between the high-voltage DC bulk capacitor
after the bridge (or to the AC side of the bridge rectifier for fast AC
reset) and the UNDER/OVER INPUT VOLTAGE pin to enable this
functionality. This function can be disabled by shorting the UNDER/
OVER INPUT VOLTAGE pin to SOURCE pin.
At power-up, after the primary bypass capacitor is charged and the
ILIM state is latched, and prior to switching, the state of the UNDER/
OVER INPUT VOLTAGE pin is checked to confirm that it is above the
brown-in and below the overvoltage shutdown thresholds.
In normal operation, if the UNDER/OVER INPUT VOLTAGE pin current
falls below the brown-out threshold and remains below brown-in for
longer than t
UV-
, the controller enters auto-restart. Switching will only
resume once the UNDER/OVER INPUT VOLTAGE pin current is above
the brown-in threshold.
In the event that the UNDER/OVER INPUT VOLTAGE pin current is
above the overvoltage threshold, the controller will also enter
auto-restart. Again, switching will only resume once the UNDER/
OVER INPUT VOLTAGE pin current has returned to within its normal
operating range.
The input line UV/OV function makes use of an internal high-voltage
MOSFET on the UNDER/OVER INPUT VOLTAGE pin to reduce power
consumption. If the cycle off-time t
OFF
is greater than 50
ms,
the
internal high-voltage MOSFET will disconnect the external 4 MΩ
resistor from the internal IC to eliminate current drawn through the
4 MΩ resistor. The line sensing function will activate again at the
beginning of the next switching cycle.
S: Has powered
up within 64 ms?
No
P: Auto-Restart
S: Powering Up
Start
P: Powered Up, Switching
S: Powering Up
P: Primary Chip
S: Secondary Chip
2s
P: Goes to Auto-Restart Off
S: Bypass Discharging
Yes
P: Switching
S: Sends Handshaking Pulses
64 ms
P: Has Received
Handshaking
Pulses
Yes
P: Stops Switching, Hands
Over Control to Secondary
No
P: Continuous Switching
S: Doesn’t Take Control
S: Has Taken
Control?
No
P: Not Switching
S: Doesn’t Take Control
Yes
End of Handshaking,
Secondary Control Mode
PI-7416-102814
Figure 7.
Primary-Secondary Handshake Flowchart.
Primary-Secondary Handshake
At start-up, the primary-side initially switches without any feedback
information (this is very similar to the operation of a standard
TOPSwitch™, TinySwitch™ or LinkSwitch™ controllers).
If no feedback signals are received during the auto-restart on-time
(t
AR
), the primary goes into auto-restart mode. Under normal
conditions, the secondary controller will power-up via the FORWARD
pin or from the OUTPUT VOLTAGE pin and take over control. From
this point onwards the secondary controls switching.
If the primary controller stops switching or does not respond to cycle
requests from the secondary during normal operation (when the
secondary has control), the handshake protocol is initiated to ensure
that the secondary is ready to assume control once the primary
begins to switch again. An additional handshake is also triggered if
the secondary detects that the primary is providing more cycles than
were requested.
5
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Rev. D 08/18
Embedded System
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