FAN3223 / FAN3224 / FAN3225 — Dual 4-A High-Speed, Low-Side Gate Drivers
FAN3223 / FAN3224 / FAN3225
Dual 4-A High-Speed, Low-Side Gate Drivers
Features
Industry-Standard Pinouts
4.5-V to 18-V Operating Range
5-A Peak Sink/Source at V
DD
= 12 V
4.3-A Sink / 2.8-A Source at V
OUT
= 6 V
Choice of TTL or CMOS Input Thresholds
Three Versions of Dual Independent Drivers:
Description
The FA N3223-25 family of dual 4 A gate dr ivers is
designed to drive N-channel enhancement- mode
MOSFETs in low -side sw itching applications by
providing high peak current pulses dur ing the short
sw itching intervals. The driver is available w ith either
TTL or CMOS input thresholds. Internal circuitry
provides an under-voltage lockout function by holding
the output LOW until the supply voltage is w ithin the
operating range. In addition, the drivers feature matched
internal propagation delays betw een A and B channels
for applications requiring dual gate drives w ith critical
timing, such as synchronous rectifiers. This also
enables connecting tw o drivers in parallel to effectively
double the current capability driving a single MOSFET.
The FA N322X drivers incorporate Miller Drive™
architecture for the final output stage. This bipolar-
MOSFET combination provides high current during the
Miller plateau stage of the MOSFET turn-on / turn-off
process to minimize sw itching loss, w hile providing rail-
to-rail voltage sw ing and reverse current capability.
The FAN3223 offers two inverting drivers and the
FA N3224 offers tw o non-inverting drivers. Each device
has dual independent enable pins that default to ON if
not connected. In the FA N3225, each channel has dual
inputs of opposite polar ity, w hich allow s configuration as
non-inverting or inverting w ith an optional enable
function using the second input. If one or both inputs are
left unconnected, internal resistors bias the inputs such
that the output is pulled LOW to hold the pow er
MOSFET OFF.
-
-
-
Dual Inverting + Enable (FAN3223)
Dual Non-Inverting + Enable (FAN3224)
Dual-Inputs (FAN3225)
Internal Resistors Turn Driver Off If No Inputs
MillerDrive™ Technology
12-ns / 9-ns Typical Rise/Fall Times (2.2-nF Load)
Under 20-ns Typical Propagation Delay Matched
w ithin 1 ns to the Other Channel
Double Current Capability by Paralleling Channels
8-Lead 3x3 mm MLP or 8-Lead SOIC Package
Rated from –40°C to +125°C Ambient
Automotive Qualified to AEC-Q100 (F085 Version)
Applications
Sw itch-Mode Pow er Supplies
High-Efficiency MOSFET Sw itching
Synchronous Rectifier Circuits
DC-to-DC Converters
Motor Control
Automotive-Qualified Systems (F085 version)
ENA
INA
GND
INB
1
2
3
4
8
ENB
OUTA
VDD
OUTB
ENA
INA
GND
INB
1
2
3
4
8
ENB
OUTA
VDD
OUTB
INA
-
1
INB+
GND
INB
-
2
3
4
8
INA+
OUTA
VDD
OUTB
A
7
6
A
7
6
+
A
-
+
B
-
7
6
5
B
5
B
5
FAN3223
FAN3224
FAN3225
Figure 1.
© 2016 Semiconductor Components Industries, LLC
December-2017, Rev. 2
Pin Configurations
Publication Order Number
FAN3224/D
FAN3223 / FAN3224 / FAN3225 — Dual 4-A High-Speed, Low-Side Gate Drivers
Package Outlines
1
8
2
1
2
3
4
8
7
6
5
7
3
6
4
5
Figure 2.
3x3 m m MLP-8 (Top View )
Figure 3.
SOIC-8 (Top View )
Thermal Characteristics
(3)
Package
8-Lead 3x3 mm Molded Leadless Package (MLP)
8-Pin Small Outline Integrated Circuit (SOIC)
Notes:
3.
4.
5.
6.
Estimates derived from thermal simulation; actual values depend on the application.
Theta_JL (
Θ
JL
): Thermal resistance between the semiconductor junction and the bottom surface of all the leads (including any
thermal pad) that are typically soldered to a PCB.
Theta_JT (
Θ
JT
): Thermal resistance between the semiconductor junction and the top surface of the package, assuming it is
held at a uniform temperature by a top-side heatsink.
Theta_JA (Θ
JA
): Thermal resistance between junction and ambient, dependent on the PCB design, heat sinking, and airflow.
The value given is for natural convection with no heatsink using a 2S2P board, as specified in JEDEC standards JESD51-2,
JESD51-5, and JESD51-7, as appropriate.
Psi_JB (
Ψ
JB
): Thermal characterization parameter providing correlation between semiconductor junction temperature and an
application circuit board reference point for the thermal environment defined in Note 6. For the MLP-8 package, the board
reference is defined as the PCB copper connected to the thermal pad and protruding from either end of the package. For the
SOIC-8 package, the board reference is defined as the PCB copper adjacent to pin 6.
Psi_JT (
Ψ
JT
): Thermal characterization parameter providing correlation between the semiconductor junction temperature and
the center of the top of the package for the thermal environment defined in Note 6.
Θ
JL(4)
1.2
38
Θ
JT(5)
64
29
Θ
JA(6)
42
87
Ψ
JB(7)
2.8
41
Ψ
JT(8)
0.7
2.3
Unit
°C/W
°C/W
7.
8.
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FAN3223 / FAN3224 / FAN3225 — Dual 4-A High-Speed, Low-Side Gate Drivers
ENA
INA
GND
INB
1
2
3
4
8
ENB
OUTA
VDD
OUTB
ENA
INA
GND
INB
1
2
3
4
8
ENB
OUTA
VDD
OUTB
INA
-
1
INB+
GND
INB
-
2
3
4
8
INA+
OUTA
VDD
OUTB
A
7
6
A
7
6
+
A
-
+
B
-
7
6
5
B
5
B
5
FAN3223
FAN3224
FAN3225
Figure 4.
Pin Assignm ents (Repeated)
Pin Definitions
Name
ENA
ENB
GND
INA
INA+
INA-
INB
INB+
INB-
OUTA
OUTB
Pin Description
Enable Input for Channel A.
Pull pin LOW to inhibit driver A. ENA has TTL thresholds for both TTL and
CMOS INx threshold.
Enable Input for Channel B.
Pull pin LOW to inhibit driver B. ENB has TTL thresholds for both TTL and
CMOS INx threshold.
Ground.
Common ground reference for input and output circuits.
Input to Channel A.
Non-Inverting Input to Channel A.
Connect to VDD to enable output.
Inverting Input to Channel A.
Connect to GND to enable output.
Input to Channel B.
Non-Inverting Input to Channel B.
Connect to VDD to enable output.
Inverting Input to Channel B.
Connect to GND to enable output.
Gate Drive Output A:
Held LOW unless required input(s) are present and V
DD
is above UVLO threshold.
Gate Drive Output B:
Held LOW unless required input(s) are present and V
DD
is above UVLO threshold.
Gate Drive Output A
(inverted from the input): Held LOW unless required input is present and V
DD
is
above UVLO threshold.
Gate Drive Output B
(inverted from the input): Held LOW unless required input is present and V
DD
is
above UVLO threshold.
Therm al Pad
(MLP only). Exposed metal on the bottom of the package; may be left floating or connected
to GND; NOT suitable for carrying current.
Supply Voltage.
Provides pow er to the IC.
OUTA
OUTB
P1
VDD
Output Logic
FAN3223 (x=A or B)
ENx
0
0
1
1
(9)
(9)
FAN3224 (x=A or B)
ENx
0
0
1
1
(9)
(9)
FAN3225 (x=A or B)
INx+
0
0
(9)
(9)
INx
0
1
1
(9)
OUTx
0
0
1
0
INx
0
0
(9)
OUTx
0
0
0
1
INx−
0
1
1
(9)
OUTx
0
0
1
0
1
(9)
0
(9)
1
1
0
(9)
1
Note:
9. Default input signal if no external connection is made.
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