NCV5700DR2G datasheet, PDF - EEWORLD Datasheet

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NCV5700DR2G: DescriptionIGBT GATE DRIVER; CategoryAnalog mixed-signal IC Drivers and interfaces; File Size329KB，18 Pages; ManufacturerON Semiconductor; Websitehttp://www.onsemi.cn

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NCV5700DR2G Overview

IGBT GATE DRIVER

NCV5700DR2G Parametric

Parameter Name	Attribute value
Brand Name	ON Semiconductor
Is it lead-free?	Lead free
Maker	ON Semiconductor
package instruction	SOP,
Manufacturer packaging code	751B-05
Reach Compliance Code	compliant
Factory Lead Time	7 weeks
Samacsys Description	IGBT Gate Drivers, High-Current, Stand-Alone
high side driver	NO
Interface integrated circuit type	BUFFER OR INVERTER BASED IGBT DRIVER
JESD-30 code	R-PDSO-G16
JESD-609 code	e3
length	9.9 mm
Humidity sensitivity level	1
Number of functions	1
Number of terminals	16
Maximum operating temperature	125 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Peak Reflow Temperature (Celsius)	260
Filter level	AEC-Q100
Maximum seat height	1.75 mm
Maximum supply voltage	20 V
Minimum supply voltage	13.2 V
Nominal supply voltage	15 V
surface mount	YES
Temperature level	AUTOMOTIVE
Terminal surface	Tin (Sn)
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	30
Disconnect time	0.075 µs
connection time	0.075 µs
width	3.9 mm
Base Number Matches	1

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NCV5700

High Current IGBT Gate

Driver

The NCV5700 is a high−current, high−performance stand−alone

IGBT driver for high power applications that include solar inverters,

motor control and uninterruptable power supplies. The device offers a

cost−effective solution by eliminating many external components.

Device protection features include Active Miller Clamp, accurate

UVLO, EN input, DESAT protection and Active Low FAULT output.

The driver also features an accurate 5.0 V output and separate high and

low (VOH and VOL) driver outputs for system design convenience.

The driver is designed to accommodate a wide voltage range of bias

supplies including unipolar and bipolar voltages. It is available in a

16−pin SOIC package.

Features

www.onsemi.com

MARKING

DIAGRAM

NCV5700DR2G

AWLYWW

SOIC−16

D SUFFIX

CASE 751B

•

High Current Output (+4/−6 A) at IGBT Miller Plateau Voltages

Low Output Impedance of VOH & VOL for Enhanced IGBT Driving

Short Propagation Delays with Accurate Matching

Direct Interface to Digital Isolator/Opto−coupler/Pulse Transformer

for Isolated Drive, Logic Compatibility for Non−isolated Drive

Active Miller Clamp to Prevent Spurious Gate Turn−on

DESAT Protection with Programmable Delay

Enable Input for Independent Driver Control

Tight UVLO Thresholds for Bias Flexibility

Wide Bias Voltage Range including Negative VEE Capability

NCV Prefix for Automotive and Other Applications Requiring

Unique Site and Control Change Requirements; AEC−Q100

Qualified and PPAP Capable, Grade 1

This Device is Pb−Free, Halogen−Free and RoHS Compliant

Motor Control

Uninterruptible Power Supplies (UPS)

Automotive Power Supplies

HEV/EV Powertrain

HEV/EV PTC Heaters

VREF

DESAT

VCC

VOH

VOL

CLAMP

GND

VEE

VCC

= Assembly Location

= Wafer Lot

= Year

= Work Week

= Pb−Free Package

PIN CONNECTIONS

VIN

VREF

FLT

GNDA

RSVD

(Top View)

16 CLAMP

15 VEEA

14 VEE

13 GND

12 VOL

11 VOH

10 VCC

DESAT

Typical Applications

ORDERING INFORMATION

See detailed ordering and shipping information on page 6 of

this data sheet.

VIN

VEE

FLT

Figure 1. Simplified Application Schematic

Semiconductor Components Industries, LLC, 2017

September, 2017 − Rev. 0

Publication Order Number:

NCV5700/D

NCV5700

Table 1. PIN FUNCTION DESCRIPTION

Pin Name

VIN

No.

I/O/x

Description

Enable input allows additional gating of VOH and VOL, and can be used when the driver output

needs to be turned off independent of the Microcontroller input.

Input signal to control the output. In applications which require galvanic isolation, VIN is generated

at the opto output, the pulse transformer secondary or the digital isolator output. There is a signal

inversion from VIN to VOH/VOL. VIN is internally clamped to 5.5 V and has a pull−up resistor of

1 MW to ensure that output is low in the absence of an input signal. A minimum pulse−width is re-

quired at VIN before VOH/VOL are activated.

5 V Reference generated within the driver is brought out to this pin for external bypassing and for

powering low bias circuits (such as digital isolators).

Fault output (active low) that allows communication to the main controller that the driver has en-

countered a fault condition and has deactivated the output. Truth Table is provided in the datasheet

to indicate conditions under which this signal is asserted. Capable of driving optos or digital isolators

when isolation is required.

This pin provides a convenient connection point for bypass capacitors (e.g REF) on the left side of

the package.

Pins not internally connected.

Reserved. No connection is allowed.

Input for detecting the desaturation of IGBT due to a fault condition. A capacitor connected to this

pin allows a programmable blanking delay every ON cycle before DESAT fault is processed, thus

preventing false triggering.

Positive bias supply for the driver. The operating range for this pin is from UVLO to the maximum. A

good quality bypassing capacitor is required from this pin to GND and should be placed close to the

pins for best results.

Driver high output that provides the appropriate drive voltage and source current to the IGBT gate.

Driver low output that provides the appropriate drive voltage and sink current to the IGBT gate. VOL

is actively pulled low during start−up and under Fault conditions.

This pin should connect to the IGBT Emitter with a short trace. All power pin bypass capacitors

should be referenced to this pin and kept at a short distance from the pin.

A negative voltage with respect to GND can be applied to this pin and that will allow VOL to go to a

negative voltage during OFF state. A good quality bypassing capacitor is needed from VEE to GND.

If a negative voltage is not applied or available, this pin must be connected to GND.

Analog version of the VEE pin for any signal trace connection. VEE and VEEA are internally con-

nected.

Provides clamping for the IGBT gate during the off period to protect it from parasitic turn−on. To be

tied directly to IGBT gate with minimum trace length for best results.

VREF

FLT

GNDA

RSVD

DESAT

6,8

VCC

VOH

VOL

GND

VEE

VEEA

CLAMP

I/O

www.onsemi.com

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