DS26324GA2+ datasheet, PDF - EEWORLD Datasheet

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DS26324GA2+: DescriptionIC TXRX LIU 256CSBGA; CategoryWireless rf/communication Telecom circuit; File Size982KB，120 Pages; ManufacturerMaxim; Websitehttps://www.maximintegrated.com/en.html; Environmental Compliance

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DS26324GA2+ Overview

IC TXRX LIU 256CSBGA

DS26324GA2+ Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Maxim
Parts packaging code	BGA
package instruction	17 X 17 MM, 1 MM PITCH, ROHS COMPLIANT, CSBGA-256
Contacts	256
Reach Compliance Code	compliant
Factory Lead Time	1 week
JESD-30 code	S-PBGA-B256
JESD-609 code	e1
length	17 mm
Humidity sensitivity level	3
Number of functions	1
Number of terminals	256
Maximum operating temperature	70 °C
Minimum operating temperature
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Package shape	SQUARE
Package form	GRID ARRAY
Peak Reflow Temperature (Celsius)	260
Certification status	Not Qualified
Maximum seat height	1.76 mm
Nominal supply voltage	3.3 V
surface mount	YES
Telecom integrated circuit types	PCM TRANSCEIVER
Temperature level	COMMERCIAL
Terminal surface	Tin/Silver/Copper (Sn/Ag/Cu)
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	30
width	17 mm
Base Number Matches	1

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19-5754; Rev 3/11

DEMO KIT AVAILABLE

DS26324

3.3V, 16-Channel, E1/T1/J1 Short-Haul Line Interface Unit

GENERAL DESCRIPTION

The DS26324 is a 16-channel short-haul line

interface unit (LIU) that supports E1/T1/J1 from a

single 3.3V power supply. A wide variety of

applications are supported through internal

impedance matching. A single bill of material can

support E1/T1/J1 that requires no external

termination. Redundancy is supported through

nonintrusive monitoring, optimal high-impedance

modes and configurable 1:1 or 1+1 backup

enhancements. An on-chip synthesizer generates the

E1/T1/J1 clock rates by a single master clock input of

various frequencies. Two clock output references are

also offered. The device is offered in a 256-pin

TE-CSBGA, the smallest package available for a

16-channel LIU.

FEATURES



16 E1, T1, or J1 Short-Haul Line Interface

Units

Independent E1, T1 or J1 Selections

Fully Internal Impedance Match Requires No

External Resistors

Software-Selectable Transmit and Receive-

Side Impedance Match

Crystal-Less Jitter Attenuator

Selectable Single-Rail and Dual-Rail Mode

and AMI or HDB3/B8ZS Line Encoding and

Decoding

Detection and Generation of AIS

Digital/Analog Loss of Signal Detection as

per T1.231, G.775 and ETS 300 233

External Master Clock Can Be Multiple of

2.048MHz or 1.544MHz for T1/J1 or E1

Operation; This Clock Will Be Internally

Adapted for T1 or E1 Usage

Receiver Signal Level Indicator from -2.5dB to

-20dB in 2.5dB Increments

Two Built-In BERT Testers for Diagnostics

8-Bit Parallel Interface Support for Intel or

Motorola Mode or a 4-Wire Serial Interface

Transmit Short-Circuit Protection

G.772 Nonintrusive Monitoring

Receive Monitor Mode Handles Combinations

of 14dB to 20dB of Resistive Attenuation

Along with 12dB to 30dB of Cable Attenuation

Specification Compliance to the Latest T1

and E1 Standards

Single 3.3V Supply with 5V Tolerant I/O

JTAG Boundary Scan as Per IEEE 1149.1

APPLICATIONS

T1 Digital Cross-Connects

ATM and Frame Relay Equipment

Wireless Base Stations

ISDN Primary Rate Interface

E1/T1/J1 Multiplexer and Channel Banks

E1/T1/J1 LAN/WAN Routers



LOSS

RPOS

RNEG

RCLK

TPOS

TNEG

TCLK

FUNCTIONAL DIAGRAM

JTAG

SOFTWARE CONTROL

AND JTAG

RTIP

RRING

TTIP

TRING

RECEIVER

TRANSMITTER



ORDERING INFORMATION

PART

TEMP RANGE PIN-PACKAGE

0°C to +70°C

-40°C to +85°C

0°C to +70°C

-40°C to +85°C

256 TE-CSBGA

DS26324G+

DS26324GN+

DS26324G

DS26324GN

+Denotes a lead(Pb)-free/RoHS compliant package.

Note:

Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device

may be simultaneously available through various sales channels. For information about device errata, click here:

www.maxim-ic.com/errata.

1 of 120

DS26324 3.3V, 16-Channel, E1/T1/J1 Short-Haul Line Interface Unit

TABLE OF CONTENTS

STANDARDS COMPLIANCE ........................................................................................................ 6

1.1 T

ELECOM

PECIFICATIONS COMPLIANCE

....................................................................................... 6

DETAILED DESCRIPTION ............................................................................................................ 7

BLOCK DIAGRAMS ...................................................................................................................... 8

PIN DESCRIPTION ...................................................................................................................... 10

FUNCTIONAL DESCRIPTION ..................................................................................................... 17

5.1 P

ORT

PERATION

...................................................................................................................... 17

5.1.1

5.1.2

5.1.3

Serial Port Operation ..................................................................................................................... 17

Parallel Port Operation ................................................................................................................... 18

Interrupt Handling .......................................................................................................................... 18

5.2

5.3

5.4

OWER

-U

P AND

ESET

.............................................................................................................. 19

ASTER

LOCK

......................................................................................................................... 19

RANSMITTER

............................................................................................................................ 20

Transmit Line Templates................................................................................................................ 22

LIU Transmit Front-End.................................................................................................................. 25

Transmit Dual-Rail Mode ............................................................................................................... 26

Transmit Single-Rail Mode ............................................................................................................. 26

Zero Suppression—B8ZS or HDB3 ................................................................................................ 26

Transmit Power-Down.................................................................................................................... 26

Transmit All Ones .......................................................................................................................... 27

Driver Fail Monitor.......................................................................................................................... 27

Receiver Impedance Matching Calibration ..................................................................................... 27

Receiver Monitor Mode .................................................................................................................. 27

Peak Detector and Slicer ............................................................................................................... 28

Receive Level Indicator .................................................................................................................. 28

Clock and Data Recovery............................................................................................................... 28

Loss of Signal ................................................................................................................................ 28

AIS ................................................................................................................................................ 29

Receive Dual-Rail Mode ................................................................................................................ 29

Receive Single-Rail Mode .............................................................................................................. 30

Bipolar Violation and Excessive Zero Detector ............................................................................... 30

5.4.1

5.4.2

5.4.3

5.4.4

5.4.5

5.4.6

5.4.7

5.4.8

5.5

ECEIVER

.................................................................................................................................. 27

5.5.1

5.5.2

5.5.3

5.5.4

5.5.5

5.5.6

5.5.7

5.5.8

5.5.9

5.5.10

5.6

5.7

5.8

ITTER

TTENUATOR

.................................................................................................................. 31

G.772 M

ONITOR

........................................................................................................................ 32

OOPBACKS

............................................................................................................................... 32

Analog Loopback ........................................................................................................................... 32

Digital Loopback ............................................................................................................................ 33

Remote Loopback .......................................................................................................................... 33

General Description ....................................................................................................................... 34

Configuration and Monitoring ......................................................................................................... 35

Receive Pattern Detection.............................................................................................................. 36

Transmit Pattern Generation .......................................................................................................... 38

5.8.1

5.8.2

5.8.3

5.9

BERT........................................................................................................................................ 34

5.9.1

5.9.2

5.9.3

5.9.4

REGISTER MAPS AND DEFINITION .......................................................................................... 39

6.1 R

EGISTER

ESCRIPTION

............................................................................................................. 48

6.1.1

6.1.2

6.1.3

6.1.4

Primary Register Bank ................................................................................................................... 48

Secondary Register Bank............................................................................................................... 63

Individual LIU Register Bank .......................................................................................................... 66

BERT Registers ............................................................................................................................. 84

JTAG BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT.................................. 91

7.1 TAP C

ONTROLLER

TATE

ACHINE

............................................................................................ 92

7.1.1

7.1.2

Test-Logic-Reset ........................................................................................................................... 92

Run-Test-Idle ................................................................................................................................. 92

2 of 120

DS26324 3.3V, 16-Channel, E1/T1/J1 Short-Haul Line Interface Unit

7.1.3

7.1.4

7.1.5

7.1.6

7.1.7

7.1.8

7.1.9

7.1.10

7.1.11

7.1.12

7.1.13

7.1.14

7.1.15

7.1.16

Select-DR-Scan ............................................................................................................................. 92

Capture-DR ................................................................................................................................... 92

Shift-DR ......................................................................................................................................... 92

Exit1-DR ........................................................................................................................................ 92

Pause-DR ...................................................................................................................................... 92

Exit2-DR ........................................................................................................................................ 92

Update-DR..................................................................................................................................... 92

Select-IR-Scan............................................................................................................................... 93

Capture-IR ..................................................................................................................................... 93

Shift-IR .......................................................................................................................................... 93

Exit1-IR.......................................................................................................................................... 93

Pause-IR ....................................................................................................................................... 93

Exit2-IR.......................................................................................................................................... 93

Update-IR ...................................................................................................................................... 93

EXTEST ........................................................................................................................................ 95

HIGHZ ........................................................................................................................................... 95

CLAMP .......................................................................................................................................... 95

SAMPLE/PRELOAD ...................................................................................................................... 95

IDCODE ........................................................................................................................................ 95

BYPASS ........................................................................................................................................ 95

Boundary Scan Register ................................................................................................................ 96

Bypass Register............................................................................................................................. 96

Identification Register .................................................................................................................... 96

7.2

NSTRUCTION

EGISTER

............................................................................................................. 95

7.2.1

7.2.2

7.2.3

7.2.4

7.2.5

7.2.6

7.3

EST

EGISTERS

....................................................................................................................... 96

7.3.1

7.3.2

7.3.3

DC ELECTRICAL CHARACTERIZATION ................................................................................... 97

8.1 DC P

OGIC

EVELS

................................................................................................................ 97

8.2 S

UPPLY

URRENT AND

UTPUT

OLTAGE

................................................................................... 97

AC TIMING CHARACTERISTICS ................................................................................................ 98

9.1 L

INE

NTERFACE

HARACTERISTICS

............................................................................................ 98

9.2 P

ARALLEL

OST

NTERFACE

IMING

HARACTERISTICS

................................................................ 99

9.3 S

ERIAL

ORT

............................................................................................................................111

9.4 S

YSTEM

IMING

........................................................................................................................112

9.5 JTAG T

IMING

............................................................................................................................114

10 PIN CONFIGURATION................................................................................................................115

PACKAGE INFORMATION .........................................................................................................116

THERMAL INFORMATION .........................................................................................................117

DATA SHEET REVISION HISTORY ...........................................................................................119

3 of 120

DS26324 3.3V, 16-Channel, E1/T1/J1 Short-Haul Line Interface Unit

LIST OF FIGURES

Figure 3-1. Block Diagram ..................................................................................................................................... 8

Figure 3-2. Receive Logic Detail ............................................................................................................................ 9

Figure 3-3. Transmit Logic Detail ........................................................................................................................... 9

Figure 5-1. Serial Port Operation for Write Access ............................................................................................... 17

Figure 5-2. Serial Port Operation for Read Access with CLKE = 0 ........................................................................ 17

Figure 5-3. Serial Port Operation for Read Access with CLKE = 1 ........................................................................ 18

Figure 5-4. Interrupt Handling Flow Diagram ........................................................................................................ 19

Figure 5-5. Prescaler PLL and Clock Generator ................................................................................................... 20

Figure 5-6. T1 Transmit Pulse Templates............................................................................................................. 23

Figure 5-7. E1 Transmit Pulse Templates............................................................................................................. 24

Figure 5-8. LIU Front-End .................................................................................................................................... 25

Figure 5-9. Jitter Attenuation ................................................................................................................................ 31

Figure 5-10. Analog Loopback ............................................................................................................................. 32

Figure 5-11. Digital Loopback .............................................................................................................................. 33

Figure 5-12. Remote Loopback ............................................................................................................................ 33

Figure 5-13. PRBS Synchronization State Diagram .............................................................................................. 36

Figure 5-14. Repetitive Pattern Synchronization State Diagram ............................................................................ 37

Figure 7-1. JTAG Functional Block Diagram......................................................................................................... 91

Figure 7-2. TAP Controller State Diagram ............................................................................................................ 94

Figure 9-1. Intel Nonmuxed Read Cycle ............................................................................................................. 100

Figure 9-2. Intel Mux Read Cycle ....................................................................................................................... 101

Figure 9-3. Intel Nonmux Write Cycle ................................................................................................................. 103

Figure 9-4. Intel Mux Write Cycle ....................................................................................................................... 104

Figure 9-5. Motorola Nonmux Read Cycle.......................................................................................................... 106

Figure 9-6. Motorola Mux Read Cycle ................................................................................................................ 107

Figure 9-7. Motorola Nonmux Write Cycle .......................................................................................................... 109

Figure 9-8. Motorola Mux Write Cycle ................................................................................................................ 110

Figure 9-9. Serial Bus Timing Write Operation.................................................................................................... 111

Figure 9-10. Serial Bus Timing Read Operation with CLKE = 0 .......................................................................... 111

Figure 9-11. Serial Bus Timing Read Operation with CLKE = 1 .......................................................................... 111

Figure 9-12. Transmitter Systems Timing ........................................................................................................... 112

Figure 9-13. Receiver Systems Timing ............................................................................................................... 113

Figure 9-14. JTAG Timing .................................................................................................................................. 114

Figure 10-1. 256-Ball TE-CSBGA....................................................................................................................... 115

4 of 120

DS26324 3.3V, 16-Channel, E1/T1/J1 Short-Haul Line Interface Unit

LIST OF TABLES

Table 4-1. Pin Descriptions .................................................................................................................................. 10

Table 5-1. Parallel Port Mode Selection and Pin Functions................................................................................... 18

Table 5-2. Telecommunications Specification Compliance for DS26324 Transmitters........................................... 21

Table 5-3. Registers Related to Control of DS26324 Transmitters ........................................................................ 21

Table 5-4. Template Selections for Short-Haul Mode............................................................................................ 22

Table 5-6. LIU Front-End Values .......................................................................................................................... 26

Table 5-7. Loss Criteria ANSI T1.231, ITU-T G.775, and ETS 300 233 Specifications .......................................... 28

Table 5-8. AIS Criteria ANSI T1.231, ITU-T G.775, and ETS 300 233 Specifications ............................................ 29

Table 5-9. AIS Detection and Reset Criteria for DS26324..................................................................................... 29

Table 5-10. Registers Related to AIS Detection.................................................................................................... 29

Table 5-11. BPV, Code Violation, and Excessive Zero Error Reporting ................................................................. 30

Table 5-12. Pseudorandom Pattern Generation ................................................................................................... 35

Table 5-13. Repetitive Pattern Generation............................................................................................................ 35

Table 6-1. Primary Register Set ........................................................................................................................... 40

Table 6-2. Secondary Register Set....................................................................................................................... 41

Table 6-3. Individual LIU Register Set .................................................................................................................. 42

Table 6-4. BERT Register Set .............................................................................................................................. 43

Table 6-5. Primary Register Set Bit Map .............................................................................................................. 44

Table 6-6. Secondary Register Set Bit Map .......................................................................................................... 45

Table 6-7. Individual LIU Register Set Bit Map ..................................................................................................... 46

Table 6-8. BERT Register Bit Map ....................................................................................................................... 47

Table 6-9. G.772 Monitoring Control (LIU 1) ......................................................................................................... 54

Table 6-10. G.772 Monitoring Control (LIU 9) ....................................................................................................... 54

Table 6-11. TST Template Select Transmitter Register (LIUs 1–8) ....................................................................... 59

Table 6-12. TST Template Select Transmitter Register (LIUs 9–16) ..................................................................... 59

Table 6-13. Template Selection............................................................................................................................ 60

Table 6-14. Address Pointer Bank Selection ........................................................................................................ 63

Table 6-15. DS26324 MCLK Selections ............................................................................................................... 69

Table 6-16. Receiver Sensitivity/Monitor Mode Gain Selection ............................................................................. 73

Table 6-17. Receiver Signal Level ........................................................................................................................ 75

Table 6-18. Bit Error Rate Transceiver Select for Channels 1–8 ........................................................................... 79

Table 6-19. Bit Error Rate Transceiver Select for Channels 9–16 ......................................................................... 79

Table 6-20. PLL Clock Select ............................................................................................................................... 82

Table 6-21. Clock A Select................................................................................................................................... 82

Table 7-1. Instruction Codes for IEEE 1149.1 Architecture ................................................................................... 95

Table 7-2. ID Code Structure ............................................................................................................................... 96

Table 7-3. Device ID Codes ................................................................................................................................. 96

Table 8-1. Recommended DC Operating Conditions ............................................................................................ 97

Table 8-2. Pin Capacitance .................................................................................................................................. 97

Table 8-3. DC Characteristics .............................................................................................................................. 97

Table 9-1. Transmitter Characteristics.................................................................................................................. 98

Table 9-2. Receiver Characteristics...................................................................................................................... 98

Table 9-3. Intel Read Mode Characteristics .......................................................................................................... 99

Table 9-4. Intel Write Cycle Characteristics ........................................................................................................ 102

Table 9-5. Motorola Read Cycle Characteristics ................................................................................................. 105

Table 9-6. Motorola Write Cycle Characteristics ................................................................................................. 108

Table 9-7. Serial Port Timing Characteristics...................................................................................................... 111

Table 9-8. Transmitter System Timing................................................................................................................ 112

Table 9-9. Receiver System Timing.................................................................................................................... 113

Table 9-10. JTAG Timing Characteristics ........................................................................................................... 114

Table 12-1. Thermal Characteristics................................................................................................................... 117

Table 12-2. Package Power Dissipation (for Thermal Considerations) ................................................................ 117

Table 12-3. Per-Channel Power-Down Savings (for Thermal Considerations)..................................................... 118

5 of 120

DS26324GA2+ Related Products

	DS26324GA2+	DS26324GNA2+	DS26324GN+T&R;
Description	IC TXRX LIU 256CSBGA	IC interface line 16ch 256-csbga	IC LIU E1/T1/J1 3.3V 256-CSBGA
Is it lead-free?	Lead free	Lead free	-
Is it Rohs certified?	conform to	conform to	-
Maker	Maxim	Maxim	-
Parts packaging code	BGA	BGA	-
package instruction	17 X 17 MM, 1 MM PITCH, ROHS COMPLIANT, CSBGA-256	17 X 17 MM, 1 MM PITCH, ROHS COMPLIANT, CSBGA-256	-
Contacts	256	256	-
Reach Compliance Code	compliant	compliant	-
JESD-30 code	S-PBGA-B256	S-PBGA-B256	-
JESD-609 code	e1	e1	-
length	17 mm	17 mm	-
Humidity sensitivity level	3	3	-
Number of functions	1	1	-
Number of terminals	256	256	-
Maximum operating temperature	70 °C	85 °C	-
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	-
encapsulated code	BGA	BGA	-
Package shape	SQUARE	SQUARE	-
Package form	GRID ARRAY	GRID ARRAY	-
Peak Reflow Temperature (Celsius)	260	260	-
Certification status	Not Qualified	Not Qualified	-
Maximum seat height	1.76 mm	1.76 mm	-
Nominal supply voltage	3.3 V	3.3 V	-
surface mount	YES	YES	-
Telecom integrated circuit types	PCM TRANSCEIVER	PCM TRANSCEIVER	-
Temperature level	COMMERCIAL	INDUSTRIAL	-
Terminal surface	Tin/Silver/Copper (Sn/Ag/Cu)	Tin/Silver/Copper (Sn/Ag/Cu)	-
Terminal form	BALL	BALL	-
Terminal pitch	1 mm	1 mm	-
Terminal location	BOTTOM	BOTTOM	-
Maximum time at peak reflow temperature	30	NOT SPECIFIED	-
width	17 mm	17 mm	-
Base Number Matches	1	1	-

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