IR3092PbF
DATA SHEET
2 PHASE OPTERON, ATHLON, OR VR10.X CONTROL IC
DESCRIPTION
The IR3092 Control IC provides a full featured, single chip solution to implement robust power conversion
solutions for three different microprocessor families; 1) AMD Opteron, 2) AMD Athlon or 3) Intel VR10.X
family of processors. The user can select the appropriate VID range with a single pin. PWM Control and 2
phase gate drive functions are integrated into a single IC. In addition to CPU power, the IR3092 offers a
compact, efficient solution for high current POL converters.
FEATURES
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5 bit or 6 bit VID with 0.5% overall system accuracy
Selectable VID Code for AMD Opteron, AMD Athlon or Intel VR10.X
Programmable Slew Rate response to “On-the-Fly” VID Code Changes
3.5A Gate Drive Capability
Programmable 100KHz to 540KHz oscillator
Programmable Voltage Positioning (can be disabled)
Programmable Softstart
Programmable Hiccup Over-Current Protection with Delay to prevent false triggering
Simplified Powergood provides indication of proper operation and avoids false triggering
Operates up to 21V input with 7.8V Under-Voltage Lockout
5V UVL with 4.3V Under-Voltage Lockout threshold
Adjustable Voltage, 150mA Bias Regulator provides MOSFET Drive Voltage
Enable Input
OVP Output
Available in a 48L MLPQ package
ORDERING INFORMATION
DEVICE
IR3092MTRPbF
x
IR3092MPbF
ORDER QUANTITY
3000 per Reel
100 piece strips
PACKAGE INFORMATION
Page 1 of 37
LGND
SETBIAS
VCC
NC
NC
BIASOUT
PWRGD
CSINP2
NC
VID_SEL
NC
NC
VID3
VID4
ROSC
VOSNS-
OCSET
VDAC
VDRP
FB
EAOUT
SS/DEL
SCOMP
NC
VID2
VID1
VID0
VID5
NC
NC
ENABLE
OVP
CSINP1
CSINM
NC
VCCH1
IR3092
48LD MLPQ
GAT EH1
PGND1
GAT EL1
VCCL
5VUVL
GAT EL2
PGND2
GAT EH2
VCCH2
NC
NC
NC
48L MLPQ
(7 x 7 mm Body)
o
JA
= 27 C/W
09/07/05
IR3092PbF
PIN DESCRIPTION
PIN# PIN SYMBOL PIN DESCRIPTION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16-17
18
19
20
21
22
23-27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43-44
45
46
47
48
VID3
VID4
ROSC
VOSNS-
OCSET
VDAC
VDRP
FB
EAOUT
SS/DEL
SCOMP
N/C
LGND
SETBIAS
VCC
N/C
BIASOUT
PWRGD
CSINP2
N/C
VID_SEL
N/C
VCCH2
GATEH2
PGND2
GATEL2
5VUVL
VCCL
GATEL1
PGND1
GATEH1
VCCH1
NC
CSINM1
CSINP1
OVP
ENABLE
N/C
VID5
VID0
VID1
VID2
Inputs to VID D to A Converter
Inputs to VID D to A Converter
Connect a resistor to VOSNS- to program oscillator frequency and FB, OCSET, BBFB, and VDAC bias currents
Remote Sense Input. Connect to ground at the Load.
Programs the hiccup over-current threshold through an external resistor tied to VDAC and an internal current
source.
Regulated voltage programmed by the VID inputs. Current Sensing and Over Current Protection are referenced
to this pin. Connect an external RC network to VOSNS- to program Dynamic VID slew rate.
Buffered IIN signal. Connect an external RC network to FB to program converter output impedance
Inverting input to the Error Amplifier. Converter output voltage is offset from the VDAC voltage through an
external resistor connected to the converter output voltage at the load and an internal current source. Bias
current is a function of ROSC. Also OVPsense.
Output of the Error Amplifier
Controls Converter Softstart, Power Good, and Over-Current Timing. Connect an external capacitor to LGND to
program the timing.
Compensation for the Current Share control loop. Connect a capacitor to ground to set the control loop’s
bandwidth. Phase 2 is forced to match phase 1’s current.
No Connect.
Local Ground and IC substrate connection
External resistor to ground sets voltage at BIASOUT pin. Bias current is a function of ROSC.
Power for internal circuitry and source for BIASOUT regulator
No Connect.
150mA open-looped regulated voltage set by SETBIAS for GATE drive bias.
Open Collector output that drives low during Softstart or any fault condition. Connect external pull-up.
Non-inverting input to the Phase 2 Current Sense Amplifier.
No Connect.
Ground Selects VR10 VID, Float Selects OPTERON VID, VCC Selects ATHLON VID
No Connect.
Power for Phase 2 High-Side Gate Driver
Phase 2 High-Side Gate Driver Output and input to GATEL2 non-overlap comparator.
Return for Phase 2 Gate Drivers
Phase 2 Low-Side Gate Driver Output and input to GATEH2 non-overlap comparator.
Can be used to monitor the driver supply voltage or 5V supply voltage when converting from 5V. An under
voltage condition initiates Soft Start.
Power for Phase 1 and 2 Low-Side Gate Drivers.
Phase 1 Low-Side Gate Driver Output and input to GATEH1 non-overlap comparator.
Return for Phase 1 Gate Drivers
Phase 1 High-Side Gate Driver Output and input to GATEL1 non-overlap comparator.
Power for Phase 1 High-Side Gate Driver
Not connected
Inverting input to the Phase 1Current Sense Amplifier.
Non-inverting input to the Current Sense Amplifier.
Output that drives high during an Over-Voltage condition.
Enable Input. A logic low applied to this pin puts the IC into Fault mode.
No Connect.
Inputs to VID D to A Converter
Inputs to VID D to A Converter
Inputs to VID D to A Converter
Inputs to VID D to A Converter
Page 2 of 37
09/07/05
IR3092PbF
ABSOLUTE MAXIMUM RATINGS
Operating Junction Temperature……………..150 C
o
o
Storage Temperature Range………………….-65 C to 150 C
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
NAME
VID3
VID4
ROSC
VOSNS-
OCSET
VDAC
VDRP
FB
EAOUT
SS/DEL
SCOMP
N/C
LGND
SETBIAS
VCC
N/C
N/C
BIASOUT
PWRGD
CSINP2
N/C
VID_SEL
N/C
N/C
N/C
N/C
N/C
VCCH2
GATEH2
PGND2
GATEL2
5VUVL
VCCL
GATEL1
PGND1
GATEH1
VCCH1
N/C
CSINM1
CSINP1
OVP
ENABLE
N/C
N/C
VID5
VID0
VID1
VID2
VMAX
30V
30V
30V
0.5V
30V
30V
30V
30V
10V
30V
30V
n/a
n/a
30V
30V
n/a
n/a
30V
30V
30V
n/a
30V
n/a
n/a
n/a
n/a
n/a
30V
30V
0.3V
30V
30V
30V
30V
0.3V
30V
30V
n/a
30V
30V
30V
30V
n/a
n/a
30V
30V
30V
30V
VMIN
-0.3V
-0.3V
-0.5V
-0.5V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
n/a
n/a
-0.3V
-0.3V
n/a
n/a
-0.3V
-0.3V
-0.3V
n/a
-0.3V
n/a
n/a
n/a
n/a
n/a
-0.3V
-0.3V DC, -2V for 100ns
-0.3V
-0.3V DC, -2V for 100ns
-0.3V
-0.3V
-0.3V DC, -2V for 100ns
-0.3V
-0.3V DC, -2V for 100ns
-0.3V
n/a
-0.3V
-0.3V
-0.3V
-0.3V
n/a
n/a
-0.3V
-0.3V
-0.3V
-0.3V
ISOURCE
1mA
1mA
1mA
10mA
1mA
1mA
5mA
1mA
10mA
1mA
5mA
n/a
50mA
1mA
1mA
n/a
n/a
250mA
1mA
250mA
n/a
1mA
n/a
n/a
n/a
n/a
n/a
n/a
3A for 100ns, 200mA DC
3A for 100ns, 200mA DC
3A for 100ns, 200mA DC
1mA
n/a
3A for 100ns, 200mA DC
3A for 100ns, 200mA DC
3A for 100ns, 200mA DC
n/a
n/a
250mA
250mA
1mA
1mA
n/a
n/a
1mA
1mA
1mA
1mA
ISINK
1mA
1mA
1mA
10mA
1mA
1mA
5mA
1mA
20mA
1mA
5mA
n/a
1mA
1mA
250mA
n/a
n/a
1mA
20mA
1mA
n/a
1mA
n/a
n/a
n/a
n/a
n/a
3A for 100ns, 200mA DC
3A for 100ns, 200mA DC
n/a
3A for 100ns, 200mA DC
1mA
3A for 100ns, 200mA DC
3A for 100ns, 200mA DC
n/a
3A for 100ns, 200mA DC
3A for 100ns, 200mA DC
n/a
1mA
1mA
1mA
1mA
n/a
n/a
1mA
1mA
1mA
1mA
o
Page 3 of 37
09/07/05
IR3092PbF
ELECTRICAL SPECIFICATIONS
Unless otherwise specified, these specifications apply over: 7.3V
V
CC
21V, 4V
V
CCL
14V,
o
o
4V
V
CCHX
28V, C
GATEHX
=3.3nF, C
GATELX
=6.8nF, 0 C
T
J
125 C
PARAMETER
VDAC Reference
System Set-Point Accuracy
TEST CONDITION
-0.3V
92616- 9 &RQQHFW )% WR
EAOUT, Measure V(EAOUT) –
V(VOSNS-) deviation from Table 1.
Applies to all VID codes.
R
ROSC
= 42k
9'$& 2&6(7
R
ROSC
= 42k
9'$& 2&6(7
VID_SEL=0, Referenced to VOSNS-
VID_SEL=Float, Referenced to
VOSNS-
MIN
TYP
0.5
MAX
UNIT
%
Source Current
Sink Current
VID Input Threshold, INTEL
VID Input Threshold, AMD
VID_SEL OPTERON
Threshold
VID_SEL ATHLON Threshold
VID_SEL Float Voltage
VID_SEL Pull-up Resistance
VID_SEL Pull-down
Resistance
VID Pull-up Current
VID Float Voltage
VID = 11111 Fault Blanking
Error Amplifier
Input Offset Voltage
56
50
0.4
1.3
1.0
3.0
2.1
30
60
9
4.5
0.5
-5
62
58
0.6
1.5
1.2
3.4
2.6
60
190
15
4.9
1.7
-1
71
67
0.8
1.7
1.4
3.8
3.2
100
375
27
5.2
4.1
3
PA
PA
V
V
V
V
V
k
k
PA
V
Ps
mV
Tracks ATHLON threshold
V(VID_SEL)<2.1V
V(VID_SEL)>3.2V
VID0-5 = 1V
Referenced to LGND
Delay to PWRGD assertion
Connect FB to EAOUT, Measure
V(EAOUT)-V(VDAC). From Table 1.
Applies to all VID codes and -0.3V
VOSNS-
9 1RWH
R
ROSC
= 42k
Note 1
Note 1
Note 1, 50mV FB signal
FB Bias Current
DC Gain
Gain-Bandwidth Product
Slew Rate
Source Current
Sink Current
Max Voltage
Min Voltage
VDRP Buffer Amplifier
Positioning Offset Voltage
Output Voltage Range
Source Current
Sink Current
28
90
4
280
.75
4.5
30.5
100
7
1.25
380
1.0
4.9
90
0
33
105
PA
dB
MHz
V/Ps
PA
mA
V
mV
mV
V
mA
PA
500
1.5
5.3
150
125
3.75
20
400
V(VDRP) – V(VDAC) with
CSINMX=CSINPX=0, Note 1.
-125
0.2
5
200
10
280
Page 4 of 37
09/07/05
IR3092PbF
PARAMETER
Oscillator
Switching Frequency
Phase1 to Phase2 Shift
BIASOUT Regulator
SETBIAS Bias Current
Set Point Accuracy
BIASOUT Dropout Voltage
BIASOUT Current Limit
Soft Start and Delay
SS/DEL to FB Input Offset
Voltage
Charge Current
Hiccup Discharge Current
OC Discharge Current
Charge/Discharge Current
Ratio
Charge Voltage
Delay Comparator Threshold
Delay Comparator Hysteresis
Discharge Comparator
Threshold
Over-Current Comparator
Input Offset Voltage
OCSET Bias Current
Max OCSET Set Point
Under-Voltage Lockout
VCC Start Threshold
VCC Stop Threshold
VCC Hysteresis
5VUVL Start Threshold
5VUVL Stop Threshold
5VUVL Hysteresis
5VUVL Input Resistance
PWRGD Output
Output Voltage
Leakage Current
Enable Input
Threshold, INTEL
Threshold, AMD
Input Resistance
Pull-up Voltage
TEST CONDITION
R
ROSC
= 42k
GATEH1 rise to GATEH2 rise
R
ROSC
= 42k
V(SETBIAS)-V(BIASOUT) @ 100mA
I(BIASOUT)=100mA,Threshold when
V(SETBIAS)-V(BIASOUT)=0.45V
MIN
160
155
105
0.1
1.2
150
With FB = 0V, adjust V(SS/DEL) until
EAOUT drives high
0.8
25
2.5
25
9
3.8
200
15
200
TYP
200
170
115
0.3
1.8
300
1.3
55
5.5
45
10
4.0
240
30
260
MAX
240
190
125
0.55
2.5
450
1.8
75
7.5
70
11
4.2
280
45
350
UNIT
kHz
°
PA
V
V
mA
V
PA
PA
PA
PA/PA
V
mV
mV
mV
Relative to Charge Voltage
V(OCSET)-V(VDAC),
CSIN=CSINP1=CSINP2, Note 1.
R
ROSC
= 42k
-125
28
3.95
7.2
6.7
450
4.05
3.92
100
24
0
30
125
33
mV
PA
V
V
V
mV
V
V
mV
k
mV
PA
V
V
k
V
Start – Stop
Start – Stop
To LGND
I(PWRGD) = 4mA
V(PWRGD) = 5.5V
VID_SEL=0, Referenced to VOSNS-
VID_SEL=Float, Referenced to
VOSNS-
7.8
7.3
500
4.3
4.125
175
36
150
0
8.3
7.8
750
4.55
4.33
250
72
300
10
0.8
1.7
20
3.7
0.4
1.3
7.5
2.4
0.6
1.5
15
3.0
Page 5 of 37
09/07/05
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