ZL40235LDG1 datasheet, PDF - EEWORLD Datasheet

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ZL40235LDG1: DescriptionLOW SKEW, LOW ADDITIVE JITTER 2; Categorylogic logic; File Size2MB，51 Pages; ManufacturerMicrosemi; Websitehttps://www.microsemi.com

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ZL40235LDG1 Overview

LOW SKEW, LOW ADDITIVE JITTER 2

ZL40235LDG1 Parametric

Parameter Name	Attribute value
Maker	Microsemi
package instruction	HVQCCN,
Reach Compliance Code	compliant
Other features	HAS ULTRA-LOW ADDITIVE JITTER LVCMOS OUTPUT
series	4000/14000/40000
Input adjustment	DIFFERENTIAL MUX
JESD-30 code	S-XQCC-N40
length	6 mm
Logic integrated circuit type	LOW SKEW CLOCK DRIVER
Number of functions	1
Number of inverted outputs
Number of terminals	40
Actual output times	10
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Output characteristics	3-STATE
Package body material	UNSPECIFIED
encapsulated code	HVQCCN
Package shape	SQUARE
Package form	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
propagation delay (tpd)	2.3 ns
Same Edge Skew-Max（tskwd）	0.04 ns
Maximum seat height	1 mm
Maximum supply voltage (Vsup)	2.625 V
Minimum supply voltage (Vsup)	2.375 V
Nominal supply voltage (Vsup)	2.5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	NO LEAD
Terminal pitch	0.5 mm
Terminal location	QUAD
width	6 mm
minfmax	1600 MHz
Base Number Matches	1

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Data Sheet

ZL40235

Low Skew, Low Additive Jitter 3 x 5 LVPECL/LVDS/HCSL

Fanout Buffer with one LVCMOS output

Features

•

3 to 1 input Multiplexer: Two inputs accept any

differential (LVPECL, HCSL, LVDS, SSTL, CML,

LVCMOS) or a single ended signal and the third

input accepts a crystal or a single ended signal

•

Five differential LVPECL/LVDS/HCSL outputs

•

One LVCMOS output

•

Ultra-low additive jitter: 24fs (integration band 12kHz

to 20MHz at 625MHz clock frequency)

•

Supports clock frequencies from 0 to 1.6GHz

•

Supports 2.5V or 3.3V power supplies for LVPECL,

LVDS or HCSL outputs

•

Supports 1.5V, 1,8V, 2.5V or 3.3V power supplies

for LVCMOS output

•

Embedded Low Drop Out (LDO) Voltage regulator

provides superior Power Supply Noise Rejection

•

Maximum output to output skew of 40ps

•

Device controlled via SPI

ZL40235LDG1

ZL40235LDF1

Ordering Information

40 pin QFN

Trays

Tape and Reel

Package size: 6 x 6 mm

-40



C to +85



Applications

•

General purpose clock distribution

Low jitter clock trees

Logic translation

Clock and data signal restoration

Wired communications: OTN, SONET/SDH, GE, 10 GE,

FC and 10G FC

PCI Express generation 1/2/3/4 clock distribution

Wireless communications

High performance microprocessor clock distribution

Test Equipment

SEL

LVCMOS_OE/

SPI_CS_b

IN_SEL0/

SPI_CLK

IN_SEL1/

SPI_SDI

SPI_SDO

SPI_CS_b

IN_SEL0

SPI_CLK

IN_SEL1

SPI_SDIO

SPI Slave

Registers:

xtal_buf_gain[7:0]

xtal_drive_level[7:0]

xtal_load_cap[7:0]

input_select[1:0]

output_drive_low

driver_type[7:0] (diff)

driver_type[9:8] (diff)

cmos_div[2:0] (cmos)

output_enable (cmos)

driver_strength (cmos)

Device ID

Bank A

OUT0_p

OUT0_n

OUT1_p

OUT1_n

Bank B

OUT_TYPE_SEL0

OUT_TYPE_SEL1

IN0_p

IN0_n

IN1_p

IN1_n

OUT2_p

OUT2_n

OUT3_p

OUT3_n

OUT4_p

OUT4_n

DIV

1to8

OUT_LVCMOS

XOUT

ZL40235

XIN

Figure 1. Functional Block Diagram

August 2017

ZL40235

Data Sheet

ZL40235

Table of Contents

Features ............................................................................................................................... 1

Applications .......................................................................................................................... 1

Table of Contents.................................................................................................................. 2

Pin Diagram .......................................................................................................................... 5

Pin Descriptions .................................................................................................................... 6

Functional Description........................................................................................................... 9

Clock Inputs .......................................................................................................................... 9

Clock Outputs ..................................................................................................................... 12

Crystal Oscillator Input ........................................................................................................ 13

Termination of unused inputs and outputs ........................................................................... 13

Power Consumption............................................................................................................ 14

Power Supply Filtering ........................................................................................................ 14

Power Supplies and Power-up Sequence............................................................................ 15

Host Interface ..................................................................................................................... 15

Typical device performance ................................................................................................ 20

Register Map ...................................................................................................................... 24

AC and DC Electrical Characteristics .................................................................................. 30

Absolute Maximum Ratings................................................................................................. 30

Recommended Operating Conditions .................................................................................. 30

Change History ................................................................................................................... 49

Package Outline ................................................................................................................. 50

August 2017

ZL40235

Data Sheet

ZL40235

List of Figures

Figure 1.

Figure 2.

Figure 3.

Figure 4.

Figure 5.

Figure 6.

Figure 7.

Figure 8.

Figure 9.

Figure 10.

Figure 11.

Figure 12.

Figure 13.

Figure 14.

Figure 15.

Figure 16.

Figure 17.

Figure 18.

Figure 19.

Figure 20.

Figure 21.

Figure 22.

Figure 23.

Figure 24.

Figure 25.

Figure 26.

Figure 27.

Figure 28.

Figure 29.

Figure 30.

Figure 31.

Figure 32.

Figure 33.

Figure 34.

Figure 35.

Figure 36.

Figure 37.

Figure 38.

Figure 39.

Figure 40.

Figure 41.

Figure 42.

Figure 43.

Figure 44.

Figure 45.

Figure 46.

Figure 47.

Functional Block Diagram ........................................................................................................................................... 1

Pin Diagram ................................................................................................................................................................ 5

Input driven by a single ended output ........................................................................................................................ 9

Input driven by DC coupled LVPECL output ................................................................................................................. 9

Input driven by DC coupled LVPECL output (alternative termination) ...................................................................... 10

Input driven by AC coupled LVPECL output ............................................................................................................... 10

Input driven by HCSL output ..................................................................................................................................... 10

Input driven by LVDS output ..................................................................................................................................... 11

Input driven by AC coupled LVDS .............................................................................................................................. 11

Input driven by an SSTL output ................................................................................................................................. 11

Termination for LVCMOS outputs ............................................................................................................................. 12

Driving a load via transformer .................................................................................................................................. 12

Crystal Oscillator Circuit............................................................................................................................................ 13

Crystal Oscillator Circuit in Hardware Controlled Mode ........................................................................................... 13

Power Supply Filtering .............................................................................................................................................. 15

Output Disable .......................................................................................................................................................... 16

Output Enable ........................................................................................................................................................... 16

SPI slave interface ..................................................................................................................................................... 17

Serial Peripheral Interface Functional Waveform

–

LSB First Mode ......................................................................... 18

Serial Peripheral Interface Functional Waveform

–

MSB First Mode........................................................................ 18

Example of the Burst Mode Operation ..................................................................................................................... 19

156.25MHz LVPECL ................................................................................................................................................... 20

1.5GHz LVPECL .......................................................................................................................................................... 20

156.25MHz LVDS ...................................................................................................................................................... 20

1.5GHz LVDS ............................................................................................................................................................. 20

100MHz HCSL............................................................................................................................................................ 20

250MHz HCSL............................................................................................................................................................ 20

I/O delay vs temperature .......................................................................................................................................... 21

PSNR vs noise frequency ........................................................................................................................................... 21

100MHz LVPECL Phase Noise ................................................................................................................................... 21

100MHz LVDS Phase Noise ....................................................................................................................................... 21

156.25MHz LVDS Phase Noise in Xtal mode ............................................................................................................. 21

100MHz HCSL Phase Noise ....................................................................................................................................... 21

156.25MHz LVPECL Phase Noise ............................................................................................................................... 22

625MHz LVPECL Phase Noise .................................................................................................................................... 22

156.25MHz LVDS Phase Noise .................................................................................................................................. 22

625MHz LVDS Phase Noise ....................................................................................................................................... 22

Output RMS jitter (12kHz to 20MHz) vs input clock slew-rate.................................................................................. 23

Output clock noise floor vs input clock slew-rate...................................................................................................... 23

Output RMS jitter (12kHz to 20MHz) vs input clock slew-rate.................................................................................. 23

Output clock noise floor vs input clock slew-rate...................................................................................................... 23

Output RMS jitter (12kHz to 20MHz) vs input clock slew-rate.................................................................................. 23

Output clock noise floor vs input clock slew-rate ..................................................................................................... 23

Differential Input Voltage Levels............................................................................................................................... 31

Differential Output Voltage Levels............................................................................................................................ 35

SPI (Serial Peripheral Interface) Timing - LSB First Mode.......................................................................................... 47

SPI (Serial Peripheral Interface) Timing - MSB First Mode ........................................................................................ 47

August 2017

ZL40235

Data Sheet

ZL40235

List of Tables

Table 1 Pin Description................................................................................................................................................................................... 6

Table 2 Input clock selection......................................................................................................................................................................... 15

Table 3 Output Type Selection ...................................................................................................................................................................... 15

Table 4 Register Map.................................................................................................................................................................................... 24

Table 5 Absolute Maximum Ratings* ........................................................................................................................................................... 30

Table 6 Recommended Operating Conditions* ............................................................................................................................................ 30

Table 7 Current consumption ....................................................................................................................................................................... 30

Table 8 Input Characteristics* ...................................................................................................................................................................... 31

Table 9 Crystal Oscillator Characteristics* ................................................................................................................................................... 32

Table 10 Power Supply Rejection Ratio for VDD = VDDO = 3.3V* ................................................................................................................ 32

Table 11 Power Supply Rejection Ratio for VDD = VDDO = 2.5V* ................................................................................................................ 33

Table 12 LVCMOS Output Characteristics for VDDO = 3.3V* ....................................................................................................................... 33

Table 13 LVCMOS Output Characteristics for VDDO = 2.5V* ....................................................................................................................... 34

Table 14 LVPECL Output Characteristics for VDDO = 3.3V* ......................................................................................................................... 35

Table 15 LVPECL Output Characteristics for VDDO = 2.5V* ......................................................................................................................... 36

Table 16 LVDS Outputs for VDDO = 3.3V* .................................................................................................................................................... 37

Table 17 LVDS Outputs for VDDO = 2.5V* .................................................................................................................................................... 38

Table 18 HCSL Outputs for VDDO = 3.3V* .................................................................................................................................................... 39

Table 19 HCSL Outputs for VDDO = 2.5V* .................................................................................................................................................... 40

Table 20 LVCMOS Output Phase Noise with 25 MHz XTAL*......................................................................................................................... 41

Table 21 LVPECL Output Phase Noise with 25 MHz XTAL* ........................................................................................................................... 41

Table 22 LVDS Output Phase Noise with 25 MHz XTAL ................................................................................................................................ 42

Table 23 HCSL Output Phase Noise with 25 MHz XTAL ................................................................................................................................ 42

Table 24 LVCMOS Output Phase Noise with 125 MHz XTAL*....................................................................................................................... 43

Table 32 AC Electrical Characteristics* - SPI (Serial Peripheral Interface) Timing ........................................................................................ 47

Table 33 6x6mm QFN Package Thermal Properties ..................................................................................................................................... 48

August 2017

ZL40235

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