Data Sheet
ZL40234
Low Skew, Low Additive Jitter, 4 Output LVPECL/LVDS/HCSL
Fanout Buffer with one LVCMOS output
Features
•
3 to 1 input Multiplexer: Two inputs accept any
differential (LVPECL, HCSL, LVDS, SSTL, CML,
LVCMOS) or a single ended signal and the third
input accepts a crystal or a single ended signal
•
Four differential LVPECL/LVDS/HCSL outputs
•
One LVCMOS output
•
Ultra-low additive jitter: 24fs (in 12kHz to 20MHz
integration band at 625MHz clock frequency)
•
Supports clock frequencies from 0 to 1.6GHz
•
Supports 2.5V or 3.3V power supplies for LVPECL,
LVDS or HCSL outputs
•
Supports 1.5V, 1.8V, 2.5V or 3.3V for LVCMOS
output
•
Embedded Low Drop Out (LDO) Voltage regulator
provides superior Power Supply Noise Rejection
•
Maximum output to output skew of 40ps
•
Device controlled via control pins
OUT_TYPE_SEL0
OUT_TYPE_SEL1
IN_SEL0
IN_SEL1
IN0_p
IN0_n
IN1_p
IN1_n
OUT_TYPE_SEL[1:0]
00
01
10
11
OUTPUTs
LVECL
LVDS
HCSL
HIGH-Z
Ordering Information
ZL40234LDG1
ZL40234LDF1
32 pin QFN
32 pin QFN
Trays
Tape and Reel
Package size: 5 x 5 mm
-40
C to +85
C
Applications
•
•
•
•
•
•
•
•
•
General purpose clock distribution
Low jitter clock trees
Logic translation
Clock and data signal restoration
Wired communications: OTN, SONET/SDH, GE, 10 GE,
FC and 10G FC
PCI Express generation 1/2/3/4 clock distribution
Wireless communications
High performance microprocessor clock distribution
Test Equipment
OUT0_p
OUT0_n
OUT1_p
OUT1_n
OUT2_p
OUT2_n
ZL40234
XOUT
OUT3_p
OUT3_n
XIN
LVCMOS_OE
Synchronous
OE
OUT_LVCMOS
Figure 1. Functional Block Diagram
August 2017
© 2017 Microsemi Corporation
ZL40234
1
Data Sheet
ZL40234
Table of Contents
Features ............................................................................................................................... 1
Applications .......................................................................................................................... 1
Table of Contents.................................................................................................................. 2
Pin Diagram .......................................................................................................................... 5
Pin Descriptions .................................................................................................................... 6
Functional Description........................................................................................................... 8
Clock Inputs .......................................................................................................................... 8
Clock Outputs ..................................................................................................................... 11
Crystal Oscillator Input ........................................................................................................ 12
Termination of unused inputs and outputs ........................................................................... 12
Power Consumption............................................................................................................ 12
Power Supply Filtering ........................................................................................................ 13
Power Supplies and Power-up Sequence............................................................................ 13
Device Control .................................................................................................................... 14
Typical device performance ................................................................................................ 16
AC and DC Electrical Characteristics .................................................................................. 20
Absolute Maximum Ratings................................................................................................. 20
Recommended Operating Conditions .................................................................................. 20
Change History ................................................................................................................... 34
Package Outline ................................................................................................................. 35
August 2017
© 2017 Microsemi Corporation
ZL40234
2
Data Sheet
ZL40234
List of Figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Functional Block Diagram ........................................................................................................................................... 1
Pin Diagram ................................................................................................................................................................ 5
Input driven by a single ended output ........................................................................................................................ 8
Input driven by DC coupled LVPECL output ................................................................................................................. 8
Input driven by DC coupled LVPECL output (alternative termination) ........................................................................ 9
Input driven by AC coupled LVPECL output ................................................................................................................. 9
Input driven by HCSL output ....................................................................................................................................... 9
Input driven by LVDS output ..................................................................................................................................... 10
Input driven by AC coupled LVDS .............................................................................................................................. 10
Input driven by an SSTL output ................................................................................................................................. 10
Termination for LVCMOS outputs ............................................................................................................................. 11
Driving a load via transformer .................................................................................................................................. 11
Crystal Oscillator Circuit............................................................................................................................................ 12
Power Supply Filtering .............................................................................................................................................. 13
Output Disable .......................................................................................................................................................... 14
Output Enable ........................................................................................................................................................... 15
156.25MHz LVPECL ................................................................................................................................................... 16
1.5GHz LVPECL .......................................................................................................................................................... 16
156.25MHz LVDS ...................................................................................................................................................... 16
1.5GHz LVDS ............................................................................................................................................................. 16
100MHz HCSL............................................................................................................................................................ 16
250MHz HCSL............................................................................................................................................................ 16
I/O delay vs temperature .......................................................................................................................................... 17
PSNR vs noise frequency ........................................................................................................................................... 17
100MHz LVPECL Phase Noise ................................................................................................................................... 17
100MHz LVDS Phase Noise ....................................................................................................................................... 17
25MHz LVDS Phase Noise in Xtal mode .................................................................................................................... 17
100MHz HCSL Phase Noise ....................................................................................................................................... 17
156.25MHz LVPECL Phase Noise ............................................................................................................................... 18
625MHz LVPECL Phase Noise .................................................................................................................................... 18
156.25MHz LVDS Phase Noise .................................................................................................................................. 18
625MHz LVDS Phase Noise ....................................................................................................................................... 18
Output RMS jitter (12kHz to 20MHz) vs input clock slew-rate.................................................................................. 19
Output clock noise floor vs input clock slew-rate...................................................................................................... 19
Output RMS jitter (12kHz to 20MHz) vs input clock slew-rate.................................................................................. 19
Output clock noise floor vs input clock slew-rate...................................................................................................... 19
Output RMS jitter (12kHz to 20MHz) vs input clock slew-rate.................................................................................. 19
Output clock noise floor vs input clock slew-rate ..................................................................................................... 19
Differential Input Voltage Levels............................................................................................................................... 21
Differential Output Voltage Levels............................................................................................................................ 25
August 2017
© 2017 Microsemi Corporation
ZL40234
3
Data Sheet
ZL40234
List of Tables
Table 1 Pin Descriptions ................................................................................................................................................................................. 6
Table 2 Input clock selection......................................................................................................................................................................... 14
Table 3 Output Type Selection ...................................................................................................................................................................... 14
Table 4 Absolute Maximum Ratings* ........................................................................................................................................................... 20
Table 5 Recommended Operating Conditions* ............................................................................................................................................ 20
Table 6 Current consumption ....................................................................................................................................................................... 20
Table 7 Input Characteristics* ...................................................................................................................................................................... 21
Table 8 Crystal Oscillator Characteristics* ................................................................................................................................................... 22
Table 9 Power Supply Rejection Ratio for VDD = VDDO = 3.3V* .................................................................................................................. 22
Table 10 Power Supply Rejection Ratio for VDD = VDDO = 2.5V* ................................................................................................................ 23
Table 11 LVCMOS Output Characteristics for VDDO = 3.3V* ....................................................................................................................... 23
Table 12 LVCMOS Output Characteristics for VDDO = 2.5V* ....................................................................................................................... 24
Table 13 LVPECL Output Characteristics for VDDO = 3.3V* ......................................................................................................................... 25
Table 14 LVPECL Output Characteristics for VDDO = 2.5V* ......................................................................................................................... 26
Table 15 LVDS Outputs for VDDO = 3.3V* .................................................................................................................................................... 27
Table 16 LVDS Outputs for VDDO = 2.5V* .................................................................................................................................................... 28
Table 17 HCSL Outputs for VDDO = 3.3V* .................................................................................................................................................... 29
Table 18 HCSL Outputs for VDDO = 2.5V* .................................................................................................................................................... 30
Table 24 5x5mm QFN Package Thermal Properties ..................................................................................................................................... 33
August 2017
© 2017 Microsemi Corporation
ZL40234
4
Data Sheet
ZL40234
Pin Diagram
The device is packaged in a 5x5mm 32-pin QFN.
OUT_TYPE_SEL1
VDD_LVCMOS
OUT_LVCMOS
LVCMOS_OE
Pin#1
Corner
IN1_p
IN1_n
VDD
32
31
30
29
28
27
26
NC1
25
GND
1
24
GND
VDDO_A
2
23
VDDO_B
OUT0_p
3
22
OUT2_p
OUT0_n
4
21
OUT2_n
Exposed GND Pad 3.1 x 3.1 mm
VDDO_A
5
20
VDDO_B
OUT1_p
6
19
OUT3_p
OUT1_n
7
18
OUT3_n
GND
8
17
GND
9
10
11
12
13
14
15
16
OUT_TYPE_SEL0
XOUT
IN_SEL0
Figure 2. Pin Diagram
August 2017
© 2017 Microsemi Corporation
ZL40234
IN_SEL1
IN0_p
VDD
XIN
IN0_n
5
京公网安备 11010802033920号
EEWORLD
