other countries. The PowerPC name and logo are registered trademarks of IBM Corp. and used under license. All other trademarks are the property of their respective owners.
DS112 (v3.1) August 30, 2010
Product Specification
www.xilinx.com
1
R
Virtex-4 Family Overview
Table 1:
Virtex-4 FPGA Family Members
(Continued)
Configurable Logic Blocks (CLBs)
(1)
Array
(3)
Row x Col
Logic
Cells
Block RAM
Ethernet
MACs
RocketIO
Transceiver
Blocks
Total Max
I/O
User
Banks I/O
Device
XC4VSX25
XC4VSX35
XC4VSX55
XC4VFX12
XC4VFX20
XC4VFX40
XC4VFX60
XC4VFX100
XC4VFX140
Slices
PowerPC
Max
Max
Processor
Distributed
XtremeDSP
18 Kb
Block
Slices
(2)
Blocks RAM (Kb)
DCMs PMCDs
Blocks
RAM (Kb)
64 x 40
96 x 40
128 x 48
64 x 24
64 x 36
96 x 52
128 x 52
160 x 68
192 x 84
23,040
34,560
55,296
12,312
19,224
41,904
56,880
94,896
10,240
15,360
24,576
5,472
8,544
18,624
25,280
42,176
160
240
384
86
134
291
395
659
987
128
192
512
32
32
48
128
160
192
128
192
320
36
68
144
232
376
552
2,304
3,456
5,760
648
1,224
2,592
4,176
6,768
9,936
4
8
8
4
4
8
12
12
20
0
4
4
0
0
4
8
8
8
N/A
N/A
N/A
1
1
2
2
2
2
N/A
N/A
N/A
2
2
4
4
4
4
N/A
N/A
N/A
N/A
8
12
16
20
24
9
11
13
9
9
11
13
15
17
320
448
640
320
320
448
576
768
896
142,128 63,168
Notes:
1.
One CLB = Four Slices = Maximum of 64 bits.
2.
Each XtremeDSP slice contains one 18 x 18 multiplier, an adder, and an accumulator
3.
Some of the row/column array is used by the processors in the FX devices.
System Blocks Common to All Virtex-4 Families
Xesium Clock Technology
•
Up to twenty Digital Clock Manager (DCM) modules
-
-
-
-
-
-
-
-
-
Precision clock deskew and phase shift
Flexible frequency synthesis
Dual operating modes to ease performance trade-off
decisions
Improved maximum input/output frequency
Improved phase shifting resolution
Reduced output jitter
Low-power operation
Enhanced phase detectors
Wide phase shift range
500 MHz XtremeDSP Slices
•
•
•
•
•
•
Dedicated 18-bit x 18-bit multiplier,
multiply-accumulator, or multiply-adder blocks
Optional pipeline stages for enhanced performance
Optional 48-bit accumulator for multiply accumulate
(MACC) operation
Integrated adder for complex-multiply or multiply-add
operation
Cascadeable Multiply or MACC
Up to 100% speed improvement over previous
generation devices.
Up to 10 Mb of integrated block memory
Optional pipeline stages for higher performance
Multi-rate FIFO support logic
-
-
-
Full and Empty Flag support
Fully programmable AF and AE Flags
Synchronous/ Asynchronous Operation
•
•
•
•
•
•
Companion Phase-Matched Clock Divider (PMCD)
blocks
Differential clocking structure for optimized low-jitter
clocking and precise duty cycle
32 Global Clock networks
Regional I/O and Local clocks
Up to 40% speed improvement over previous
generation devices
Up to 200,000 logic cells including:
-
-
-
Up to 178,176 internal registers with clock enable
(XC4VLX200)
Up to 178,176 look-up tables (LUTs)
Logic expanding multiplexers and I/O registers
500 MHz Integrated Block Memory
•
•
•
Flexible Logic Resources
•
•
•
•
•
•
•
•
Cascadable variable shift registers or distributed
memory capability
Dual-port architecture
Independent read and write port width selection (RAM
only)
18 Kbit blocks (memory and parity/sideband memory
support)
Configurations from 16K x 1 to 512 x 36
(4K x 4 to 512 x 36 for FIFO operation)
Byte-write capability (connection to PPC405, etc.)
Dedicated cascade routing to form 32K x 1 memory
without using FPGA routing
Up to 100% speed improvement over previous
generation devices.
DS112 (v3.1) August 30, 2010
Product Specification
www.xilinx.com
2
R
Virtex-4 Family Overview
SelectIO Technology
•
•
•
•
•
•
•
Up to 960 user I/Os
Wide selections of I/O standards from 1.5V to 3.3V
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