Product Specification
DWDM 2.7G SFP Transceiver
FWLF1632xx
PRODUCT FEATURES
•
•
•
•
•
•
•
Hot-pluggable SFP footprint
Up to 2.7 Gb/s data rates
100GHz DWDM ITU Grid, C-Band
Low dispersion DFB laser with
120km reach performance
Extended link budget with APD
receiver technology
-5°C to 70°C operating case temp.
Wavelength controlled within
±0.1nm over life and temperature
APPLICATIONS
•
•
•
Amplified DWDM & SONET
networks
Bandwidth aggregation
Ring topologies with fixed and
reconfigurable OADMs
Finisar’s FWLF1632xx transceivers are Small Form Factor Pluggable
1
SFP transceivers
designed for use in Dense Wavelength-Division Multiplexing (DWDM) links, for up to
120km link lengths and up to 2.7G bit rates.
The FWLF1632xx SFP transceivers are designed for service providers deploying
SONET
2
and DWDM networking equipment in metropolitan access and core networks,
and they are also compatible to Gigabit Ethernet data rate.
The optical transceiver is compliant per the RoHS Directive 2011/65/EU. See Finisar
Application Note AN-2038 for more details.
3,4
. Basic digital diagnostic features are
implemented as described in Finisar Application Note AN-2030
5
. Enhanced diagnostic
features are available as described in the DWDM SFP MSA
6
.
PRODUCT SELECTION
FWLF1632xx
xx: 100GHz ITU Grid channel/wavelength
(please see also next page)
Finisar Corporation - August 2015
Rev B1
Page 1
FWLF1632xx Product Specification
Ordering Information
Product Code
FWLF163217
FWLF163218
FWLF163219
FWLF163220
FWLF163221
FWLF163222
FWLF163223
FWLF163224
FWLF163225
FWLF163226
FWLF163227
FWLF163228
FWLF163229
FWLF163230
FWLF163231
FWLF163232
FWLF163233
FWLF163234
FWLF163235
FWLF163236
FWLF163237
FWLF163238
FWLF163239
FWLF163240
FWLF163241
FWLF163242
FWLF163243
FWLF163244
FWLF163245
FWLF163246
FWLF163247
FWLF163248
FWLF163249
FWLF163250
FWLF163251
FWLF163252
FWLF163253
FWLF163254
FWLF163255
FWLF163256
FWLF163257
FWLF163258
FWLF163259
FWLF163260
FWLF163261
Frequency (THz)
191.7
191.8
191.9
192.0
192.1
192.2
192.3
192.4
192.5
192.6
192.7
192.8
192.9
193.0
193.1
193.2
193.3
193.4
193.5
193.6
193.7
193.8
193.9
194.0
194.1
194.2
194.3
194.4
194.5
194.6
194.7
194.8
194.9
195.0
195.1
195.2
195.3
195.4
195.5
195.6
195.7
195.8
195.9
196.0
196.1
Center Wavelength (nm)
1563.86
1563.05
1562.23
1561.42
1560.61
1559.79
1558.98
1558.17
1557.36
1556.55
1555.75
1554.94
1554.13
1553.33
1552.52
1551.72
1550.92
1550.12
1549.32
1548.51
1547.72
1546.92
1546.12
1545.32
1544.53
1543.73
1542.94
1542.14
1541.35
1540.56
1539.77
1538.98
1538.19
1537.40
1536.61
1535.82
1535.04
1534.25
1533.47
1532.68
1531.90
1531.12
1530.33
1529.55
1528.77
Finisar Corporation - August 2015
Rev B1
Page 2
FWLF1632xx Product Specification
I.
Pin Descriptions
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Symbol
V
EET
T
FAULT
T
DIS
MOD_DEF(2)
MOD_DEF(1)
MOD_DEF(0)
Rate Select
LOS
V
EER
V
EER
V
EER
RD-
RD+
V
EER
V
CCR
V
CCT
V
EET
TD+
TD-
V
EET
Name/Description
Transmitter Ground (Common with Receiver Ground)
Transmitter Fault
Transmitter Disable. Laser output disabled on high or open
Module Definition 2. Data line for Serial ID
Module Definition 1. Clock line for Serial ID
Module Definition 0. Grounded within the module
No connection required
Loss of Signal indication. Logic 0 indicates normal operation
Receiver Ground (Common with Transmitter Ground)
Receiver Ground (Common with Transmitter Ground)
Receiver Ground (Common with Transmitter Ground)
Receiver Inverted DATA out. AC Coupled
Receiver Non-inverted DATA out. AC Coupled
Receiver Ground (Common with Transmitter Ground)
Receiver Power Supply
Transmitter Power Supply
Transmitter Ground (Common with Receiver Ground)
Transmitter Non-Inverted DATA in. 100 ohm termination
between TD+ and TD-, AC Coupled thereafter
Transmitter Inverted DATA in. See TD+
Transmitter Ground (Common with Receiver Ground)
Ref.
1
2
3
3
3
4
5
1
1
1
1
1
1
Notes:
1. Circuit ground is internally isolated from chassis ground.
2. Laser output disabled on T
DIS
>2.0V or open, enabled on T
DIS
<0.8V.
3. Should be pulled up with 4.7k – 10kohms on host board to a voltage between 2.0V and 5.5V.
MOD_DEF(0) pulls line low to indicate module is plugged in.
4. Receiver achieves multi-rate operation without active control.
5. LOS is open collector output. Should be pulled up with 4.7k – 10kohms on host board to a voltage between 2.0V
and 5.5V. Logic 0 indicates normal operation; logic 1 indicates loss of signal.
VeeT
1
2
3
4
VeeT
TD-
TXFault
TD+
TX Disable
VeeT
MOD-DEF(2)
VccT
20
19
18
17
16
15
14
13
12
11
Towards
Bezel
5
6
7
8
9
10
MOD-DEF(1)
VccR
MOD-DEF(0)
VeeR
Rate Select
RD+
LOS
RD-
VeeR
VeeR
VeeR
Towards
ASIC
Diagram of Host Board Connector Block Pin Numbers and Names
Finisar Corporation - August 2015
Rev B1
Page 3
FWLF1632xx Product Specification
II.
Absolute Maximum Ratings
Parameter
Maximum Supply Voltage
Storage Temperature
Case Operating Temperature
Symbol
Vcc
T
S
T
OP
Min
-0.5
-40
-5
Typ
Max
4.7
85
70
Unit
V
°C
°C
III.
Electrical Characteristics
(T
OP
= -5 to 70
°C,
V
CC
= 3.13 to 3.50 Volts)
Symbol
Vcc
Icc
I
surge
Pmax
R
in
Vin,pp
V
D
V
EN
Vout,pp
t
r
t
f
V
LOS fault
V
LOS norm
PSR
Min
3.13
Typ
3.30
Max
3.50
380
Icc+30
1.3
Unit
V
mA
mA
W
Ω
mV
V
V
mV
ps
ps
V
V
mVpp
Ref.
Parameter
Supply Voltage
Supply Current
Inrush Current
Maximum Power
TRANSMITTER
Input differential impedance
Single ended data input swing
Transmit Disable Voltage
Transmit Enable Voltage
RECEIVER
Single ended data output swing
Data output rise time
Data output fall time
LOS Fault
LOS Normal
Power Supply Rejection
100
250
Vcc – 1.3
Vee
175
1200
Vcc
Vee+ 0.8
1000
150
150
Vcc
HOST
Vee+0.5
1
2
3
4
4
5
5
6
Vcc – 0.5
Vee
100
Notes:
1. Connected directly to TX data input pins. AC coupled thereafter.
2. Or open circuit.
3. Into 100 ohms differential termination.
4. 20 – 80 %
5. Loss of signal (LOS) is LVTTL. Logic 0 indicates normal operation; logic 1 indicates no signal detected.
6. Receiver sensitivity is compliant with power supply sinusoidal modulation of 20 Hz to 1.5 MHz up to specified
value applied through the recommended power supply filtering network.
Finisar Corporation - August 2015
Rev B1
Page 4
FWLF1632xx Product Specification
IV. Low Speed Signals
Parameter
RX_LOS Assert Level
RX_LOS Deassert Level
RX_LOS Hysteresis
RX_LOS Assert Delay
RX_LOS Negate Delay
TX_DISABLE Assert Time
t_loss_on
t_loss_off
t_off
Symbol
Min
-42
0.5
Typ
-36
-34
2
Max
-32
100
100
10
Units Notes/Conditions
dBm
dBm
dB
µsec
µsec
µsec
From detection of loss of signal
to assertion of RX_LOS
From detection of presence of
signal to negation of RX_LOS
Rising edge of TX_DISABLE to
fall of output signal below 10%
of nominal
Falling edge of TX_DISABLE
to rise of output signal above
90% of nominal. Time
indicated is under steady-state
temperature conditions.
TX_DISABLE HIGH before
TX_DISABLE set LOW
TX_Fault will assert before the
device is outside of specified
wavelength range
TX_DISABLE Negate Time
t_on
20
ms
TX_DISABLE Reset Time
TX_FAULT Assert
t_reset
10
-0.2
+0.2
µsec
nm
Finisar Corporation - August 2015
Rev B1
Page 5
DIY/Open Source Hardware
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