597GA000586DGR datasheet, PDF - EEWORLD Datasheet

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597GA000586DGR: DescriptionVCXO; DIFF/SE; QUAD FREQ; 10-810; CategoryPassive components; File Size371KB，13 Pages; ManufacturerSilicon Laboratories Inc

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597GA000586DGR Overview

VCXO; DIFF/SE; QUAD FREQ; 10-810

597GA000586DGR Parametric

Parameter Name	Attribute value
type	VCXO
Frequency - Output 1	100MHz
Frequency - Output 2	120MHz
Frequency - Output 3	130MHz
Frequency - Output 4	160MHz
Function	enable/disable
output	CMOS
Voltage - Power	2.5V
frequency stability	±20ppm
Operating temperature	-40°C ~ 85°C
Current - Power (maximum)	100mA
size/dimensions	0.276" long x 0.197" wide (7.00mm x 5.00mm)
high	0.071"（1.80mm）
Package/casing	8-SMD, no leads
Current - Power (disabled) (maximum)	75mA

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Si597

UAD

R E Q U E N C Y

O L TAG E

- C

O N T R O L L E D

RYSTAL

SCILLATOR

( V C X O ) 1 0

810 MH

Features



Available with any-frequency

output from 10 to 810 MHz



4 selectable output frequencies



3rd generation DSPLL

with

superior jitter performance



Internal fixed fundamental mode

crystal frequency ensures high

reliability and low aging

Available CMOS, LVPECL,

LVDS, and CML outputs

3.3, 2.5, and 1.8 V supply options

Industry-standard 5 x 7 mm

package and pinout

Pb-free/RoHS-compliant

–40 to +85 ºC operating range

Si5602

Applications



Ordering Information:

See page 8.



SONET/SDH (OC-3/12/48)

Networking

SD/HD SDI/3G SDI video

OTN

Clock recovery and jitter cleanup PLLs

FPGA/ASIC clock generation

Description

The Si597 quad frequency VCXO utilizes Silicon Laboratories’ advanced

DSPLL

circuitry to provide a low-jitter clock for all output frequencies. The

Si597 is available with one of four pin-selectable ouput frequencies from 10

to 810 MHz. Unlike traditional VCXOs, where a different crystal is required

for each output frequency, the Si597 uses one fixed crystal to provide a wide

range of output frequencies. This IC-based approach allows the crystal

resonator to provide exceptional frequency stability and reliability. In

addition, DSPLL clock synthesis provides supply noise rejection, simplifying

the task of generating low-jitter clocks in noisy environments. The Si597 IC-

based quad frequency VCXO is factory-configurable for a wide variety of

user specifications including frequencies, supply voltage, output format,

tuning slope, and absolute pull range (APR). Specific configurations are

factory programmed at time of shipment, thereby eliminating the long lead

times associated with custom oscillators.

Pin Assignments:

See page 7.

(Top View)

FS[1]

CLK–

GND

FS[0]

CLK+

Functional Block Diagram

P oo w e r S u p p ly F ilte rin g

P w e r S u p p ly F ilte rin g

CLK+

F ixe d

F re q u e n cy

O s cilla to r

A n y F re q u e n c y

10–810 M H z

DSPLL

C lo c k S y n th e s is

CLK-

ADC

C o n tro l

GND

FS0

FS1

Rev. 1.1 6/18

Si597

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