UltraScale Devices
Integrated 100G Ethernet
v2.3
LogiCORE IP Product Guide
Vivado Design Suite
PG165 April 4, 2018
Table of Contents
IP Facts
Chapter 1: Overview
Feature Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Licensing and Ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Chapter 2: Product Specification
Typical Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Statistics Gathering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Testability Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pause Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Resource Utilization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Attribute Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11
11
11
12
12
12
12
13
42
Chapter 3: Designing with the Core
Clocking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Protocol Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1588v2 Timestamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transceiver Selection Rules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Dynamic Reconfiguration Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
50
51
54
54
58
79
85
86
Chapter 4: Design Flow Steps
Customizing and Generating the Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Constraining the Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Synthesis and Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
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Chapter 5: Example Design
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
User Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CORE XCI Top Level Port List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Modes of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transaction Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CORE DRP Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AXI4-Lite Interface Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IEEE 802.3bj RS-FEC Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Core Bring Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Use Case for Different Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Simulating the Example Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Synthesizing and Implementing the Example Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
108
113
115
156
160
169
169
200
201
202
209
211
Appendix A: Auto-Negotiation and Link Training
Auto-Negotiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Link Training . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
Port Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
Appendix B: Upgrading
Appendix C: Debugging
Finding Help on Xilinx.com . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Debug Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Simulation Debug. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hardware Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interface Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Protocol Debug. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
229
230
231
232
234
235
Appendix D: Additional Resources and Legal Notices
Xilinx Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Documentation Navigator and Design Hubs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Please Read: Important Legal Notices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
237
237
237
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IP Facts
Introduction
The Xilinx® UltraScale™ Devices Integrated
100G Ethernet IP core provides a high
performance, low latency 100 Gb/s Ethernet
port that allows for a wide range of user
customization and statistics gathering. The
dedicated block provides both the 100G
Ethernet media access control (MAC) and
physical coding sublayer (PCS) logic with
support for
IEEE 1588-2008
[Ref 1]
one-step
and two-step hardware timestamping.
The 100G Ethernet IP core provides three
configurations: (CAUI-10) 10x10.3125G,
(CAUI-4) 4x25.78125G, and runtime switchable
between CAUI-4 and CAUI-10 mode. The 100G
Ethernet IP core is designed to the
IEEE std
802.3-2012
[Ref 2]
specification.
•
Supports 100GBASE-CR4, 100GBASE-KR4,
100GBASE-SR, 100GBASE-LR4, etc.
See
Feature Summary in Chapter 1
for a list of
additional features.
LogiCORE™ IP Facts Table
Core Specifics
Supported
Device Family
(1)
Supported User
Interfaces
Resources
Kintex® UltraScale, Virtex® UltraScale
Segmented LBUS
Performance and Resource Utilization web page
Provided with Core
Design Files
Example Design
Test Bench
Constraints File
Simulation
Model
Supported
S/W Driver
Verilog
Verilog
Verilog
Xilinx Design Constraints (XDC)
Verilog
Linux
(2)
Features
•
Supports CAUI-10, CAUI-4, and runtime
switchable between CAUI-4 and CAUI-10
modes
512-bit segmented local bus (LBUS) user
interface at ~322 MHz
32-bit interface to the serial transceiver for
CAUI-10 lanes and 80-bit interface to the
serial transceiver for CAUI-4 lanes
Optional fee-based soft 100G RS-FEC for
CAUI-4 and runtime switch CAUI-4 modes
IEEE 1588-2008
[Ref 1]
one-step and
two-step hardware timestamping at ingress
and egress at full 80-bits
Pause frame processing including priority
based flow control per
IEEE std 802.3-2012
Annex 31
[Ref 2]
Dynamic and static deskew support
Optional fee-based Auto-negotiation and
Link Training feature for CAUI-4 mode
•
•
Tested Design Flows
(3)
Design Entry
Simulation
Synthesis
Vivado® Design Suite
For supported simulators, see the
Xilinx Design Tools: Release Notes Guide.
Vivado synthesis
Support
Provided by Xilinx at the
Xilinx Support web page
Notes:
1. For a complete list of supported devices, see the Vivado IP
catalog.
•
•
2. Contact
Ethernet_mgmt@xilinx.com
for 100G Ethernet
driver early access.
3. For the supported versions of the tools, see the
Xilinx Design Tools: Release Notes Guide.
•
•
•
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Product Specification
Chapter 1
Overview
This product guide describes the function and operation of the Xilinx® UltraScale™ Devices
Integrated 100G Ethernet IP core, including how to design, customize, and implement it.
The core is designed to the
IEEE std 802.3-2012
[Ref 2]
specification with an option for
IEEE
1588-2008
[Ref 1]
hardware timestamping. The core instantiates the UltraScale Devices
Integrated 100G Ethernet. This core simplifies the design process and reduces time to
market.
Although the core is a fully-verified solution, implementing a complete design varies
depending on the configuration and functionality of the application. See
Chapter 2, Product
Specification
for details about the core.
RECOMMENDED:
For best results, previous experience building high performance, pipelined FPGA
designs using Xilinx implementation design tools and constraint files is recommended.
IMPORTANT:
CAUI-4 and switchable CAUI-10/CAUI-4 require GTY transceivers that are available in
Virtex® UltraScale and Kintex® UltraScale devices.
Feature Summary
•
•
•
•
•
•
•
•
•
One-step and two-step IEEE 1588-2008
[Ref 1]
hardware timestamping with
transparent clock and ordinary clock support
20 PCS lanes (PCSLs) for the 100G Ethernet IP core
GTY or GTH transceivers used for UltraScale devices
PCS Lane marker framing and de-framing including reordering of each PCS lane
Link status and alignment monitoring reporting
64B/66B decoding and encoding as defined in
IEEE std 802.3-2012
Clause 82
[Ref 2]
Scrambling and descrambling using x
58
+ x
39
+ 1 polynomial
Standard Inter-Packet gap (IPG) insertion and deletion as required by
IEEE std
802.3-2012
Clause 82
[Ref 2]
Optional frame check sequence (FCS) calculation and addition in the transmit direction
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