PI49FCT3805D
3.3V, 2 x 1:5 CMOS Clock Driver
Features
•
•
•
•
•
•
•
•
•
Low output skew: <200ps
Switching frequency up to 166 MHz
Fast output rise/fall time: <1.0ns
Low propagation delay: <2.5ns
Low input capacitance: <6.0pF
Balanced CMOS outputs
Industrial Temperature: –40°C to +85°C
3.3V ±10% operation, 5V Input Tolerant
Packaging (Pb-free & Green available):
– 20-pin 150-mil wide QSOP (Q)
– 20-pin 209-mil wide SSOP (H)
Description
Pericom Semiconductor’s PI49FCT3805D is composed of non-
inverting drivers. The outputs are configured into 2 groups of
one-in, five-out with independent output enable. Group B has an
extra MON output. Excellent output signals to power and ground
ratio minimize power and ground noise and also improves output
performance.
Block Diagram
OE
A
IN
A
5
OA
0Ð4
Pin Configuration
VCC
OA0
OA1
OA2
GNDA
OA3
OA4
GNDQ
MON
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
VCCB
OB0
OB1
OB2
GNDB
OB3
OB4
MON
OEB
INB
IN
B
OE
B
5
OB
0Ð4
OEA
INA
Pin Description
Pin Name
OE
X
IN
X
OA
N
, OB
N
MON
GND
V
CC
Clock Inputs
Clock Outputs
Monitor Output
Ground
Power
Deescription
Hi-Z State Output Enable Inputs (Active Low)
Truth Table
(1)
Inputs
OE
X
L
L
H
H
IN
X
L
H
L
H
OA
X
L
H
Z
Z
Outputs
MON
L
H
L
H
Note:
1. H = High Voltage Level, L = Low Voltage Level,
Z = High Impedance
11-0005
1
PS8492F
07/29/10
PI49FCT3805D
3.3V, 2 x 1:5 CMOS Clock Driver
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature .................................................................
–65°C to +150°C
Ambient Temperature with Power Applied
................................
–40°C to +85°C
Input Voltage to GND Potential (Inputs & V
CC
Only)
..................
–0.5V to 5.5V
Output Voltage to GND Potential (Outputs & I/O Only)
...–0.5V
to +V
CC
+0.5V
V
CC
Input Voltage
........................................................................
–0.5V to +4.6V
Note:
Stresses greater than those listed under MAXIMUM
RATINGS may cause permanent damage to the device.
This is a stress rating only and functional operation of
the device at these or any other conditions above those
indicated in the operational sections of this specification
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
DC Electrical Characteristics
(T
A
= –40°C to +85°C, V
CC
= 3.3V ± 0.3V)
Symbol
V
OH
Parameters
Output High Voltage
V
CC
= Min.,
V
IN
= V
IL
or V
IH
Output Low Voltage
V
CC
= Min.,
V
IN
= V
IL
or V
IH
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
High Impedance
output current
Clamp Diode Voltage
Output High Current
(4, 5)
Output Low Current
(4, 5)
Short Circuit Current
(4, 5)
Test Conditions
(1)
Min.
V
CC
-0.2
2.4
(3)
2.4
(3)
Typ.
-
3.0
3.0
-
0.2
0.3
2.0
-0.5
0.2
0.4
0.4
5.5
0.8
1
-1
1
-1
-0.7
-40
50
-60
-74
90
-100
-1.2
-100
130
-120
mA
µA
V
Max.
Units
I
OH
= -0.1mA
I
OH
= -8mA
I
OH
= -12mA
I
OH
= 0.1mA
I
OH
= 8mA
I
OH
= 12mA
Low Logic
High Logic
V
CC
= Max., V
IN
= 5.5V
V
CC
= Max., V
IN
= GND
V
CC
= Max., all
outputs disabled
V
OUT
= V
CC
V
OUT
= GND
V
OL
V
IH
V
IL
I
IH
I
IL
I
OZH
I
OZL
V
IK
I
ODH
I
ODL
I
OS
V
CC
= Min., I
IN
= -18mA
V
OUT
= 1.5V, V
IN
= V
IL
or V
IH
, V
CC
= 3.3V
V
OUT
= 1.5V, V
IN
= V
IL
or V
IH
, V
CC
= 3.3V
V
CC
= Max., V
OUT
= GND
V
Notes:
1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 3.3V, +25°C ambient and maximum loading.
3.
V
OH
= V
CC
– 0.6V
at rated current.
4. This parameter is determined by device characterization but is not production tested.
5. Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
11-0005
2
PS8492F
07/29/10
PI49FCT3805D
3.3V, 2 x 1:5 CMOS Clock Driver
Capacitance
(T
A
= 25°C, f = 1 MHz)
Parameters
(1)
Description
Input Capacitance
Output Capacitance
Test Conditions
V
IN
= 0V
V
OUT
= 0V
Typ
3.0
—
Max.
4
6
Units
pF
C
IN
C
OUT
Note:
1. This parameter is determined by device characterization but is not production tested.
Power Supply Characteristics
Parameters
I
CC
I
DD
Description
Quiescent Power
Supply Current
Dynamic Supply
Current per Output
V
CC
= Max.
Test Conditions
(1)
V
IN
= GND or V
DD
Min.
Typ.
(2)
0.1
80
Max.
30
Units
V
CC
= 3.6V,
C
L
= 15pF,
All Outputs Toggling
V
CC
= 3.6V,
C
L
= 15pF,
All Outputs Toggling,
f
i
= 133 MHz
V
CC
= 3.6V,
C
L
= 15pF,
All Outputs Toggling,
f
i
= 166 MHz
V
CC
= Max.
V
IN
= V
CC
or GND
V
IN
= V
CC
-0.6V or GND
V
IN
= V
CC
or GND
V
IN
= V
CC
-0.6V or GND
V
IN
= V
CC
-0.6V
(3)
µA
120
135
135
160
160
300
µA
mA/
MHz
100
100
120
120
45
I
C
Total Power Supply
Current
∆I
CC
Supply Current per
inputs @ TTL High
Notes:
1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device.
2. Typical values are at V
CC
= 3.3V, +25°C ambient.
3. Per TTL driven input (V
IN
=
V
CC
– 0.6V);
all other inputs at V
CC
or GND.
11-0005
3
PS8492F
07/29/10
PI49FCT3805D
3.3V, 2 x 1:5 CMOS Clock Driver
Switching Characteristics over Operating Range
Parameters
t
PLH
t
PHL
t
R
/t
F
t
SK(o)(3)
t
SK(p)(3)
t
SK(t)(3)
t
ZL
, t
ZH
,
t
LZ
, t
HZ
F
MAX
Description
Propagation Delay IN
N
to O
N
CLKn Rist/Fall Time 0.8V ~ 2.0V
Pulse Skew
Output Skew
Package Skew
Enable/Disable Time
Input Frequency
C
L
= 15pF,
133 MHz (3805D)
Test Conditions
(1)
3805D
Max.
3.0
1.5
270
270
550
5.2
133
ns
MHz
ps
ns
Units
Note:
1. These parameters are guaranteed by design
2. Series Resistor loading = 33Ω (See Test Circuit)
Switch Position
Test
Disable LOW
Enable LOW
Disable HIGH
Enable HIGH
All Other Inputs
Switch
6V
GND
Open
Definitions:
1. C
L
= Load capacitance: includes jig and probe capacitance.
2. R
T
= Termination resistance: should be equal to Z
OUT
of the Pulse
Generator.
Tests Circuit
V
CC
Enable/Disable Time Test Set-Up
6V
S
V
CC
Pulse
Generator
f = 125MHz
50Ω
33Ω
D.U.T.
C
L
15pF
Pulse
Generator
50Ω
D.U.T.
C
L
15pF
33Ω
500Ω
500Ω
11-0005
4
PS8492F
07/29/10
PI49FCT3805D
3.3V, 2 x 1:5 CMOS Clock Driver
Switching Waveforms
Propagation Delay
3V
Input
t
PLH
Output
t
PHL
1.5V
0V
V
OH
1.5V
V
OL
Oy
Ox
tSK(o)
tSK(o)
Output Skew – t
sk
(o)
3V
Input
tPLHx
tPHLx
1.5V
0V
VOH
1.5V
VOL
VOH
1.5V
tPLHy
VOL
tPHLy
Enable and Disable Times
Enable
OE
t
PZL
Output
Normally
Low
Switch
Closed
t
PZH
t
PLZ
Disable
3V
1.5V
0V
3.0V
0.3V
t
PHZ
1.5V
0V
0.3V
V
OL
V
OH
0V
tSK(o) = | tPLHy Ð tPLHx | or | tPHLy Ð tPHLx |
Pulse Skew – t
sk
(p)
Enable
OE
t
PZL
Output
Normally
Low
Switch
Closed
t
PZH
t
PLZ
Disable
3V
1.5V
0V
3.0V
0.3V
t
PHZ
1.5V
0V
0.3V
V
OL
V
OH
0V
3.0V
1.5V
Output
Normally
High
Switch
Open
3.0V
1.5V
Package Skew – t
sk
(t)
3V
Input
tPLH1
Package 1
Output
tSK(t)
tSK(t)
1.5V
tPHL1
0V
VOH
1.5V
VOL
VOH
1.5V
tPLH2
VOL
tPHL2
Output
Normally
High
Switch
Open
Package 2
Output
tSK(t) = | tPLH2 Ð tPLH1 | or | tPHL2 Ð tPHL1 |
11-0005
5
PS8492F
07/29/10
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