EEWORLDEEWORLDEEWORLD

Part Number

Search

68491-372HLF

Description
BERGSTIK II .100" DR ST
CategoryThe connector   
File Size654KB,8 Pages
ManufacturerAmphenol
Websitehttp://www.amphenol.com/
Environmental Compliance
Download Datasheet Parametric View All

68491-372HLF Online Shopping

Suppliers Part Number Price MOQ In stock  
68491-372HLF - - View Buy Now

68491-372HLF Overview

BERGSTIK II .100" DR ST

68491-372HLF Parametric

Parameter NameAttribute value
Connector typeConnector
Contact typeMale pin
Spacing - Mating0.100"(2.54mm)
Number of pins72
Number of rows2
Line spacing - patching0.100"(2.54mm)
Number of pins loadedall
styleboard to board
shieldUncovered
Installation typeThrough hole
Terminationwelding
Fastening typepush-pull
Contact Length - Mating0.255"(6.48mm)
Contact length - terminal0.120"(3.05mm)
Overall contact length0.475"(12.07mm)
Insulation height0.100"(2.54mm)
Contact shapeSquare
Contact surface treatment - matingGold or Gold, GXT™
Contact Surface Treatment Thickness - Mating50.0µin(1.27µm)
Contact Surface Preparation - Column-
Contact materialPhosphor bronze
Insulation Materials-
characteristic-
Operating temperature-
Intrusion protection-
Material flammability ratingUL94 V-0
Insulation colorblack
Rated current-
Rated voltage-
Joint stack height-
Contact Surface Treatment Thickness - Column-
application-
PDS: Rev :DH
STATUS:Released
Printed: Oct 29, 2013
msp430 program library serial series 12864 LCD
Liquid crystal is one of the most commonly used display devices in the single-chip microcomputer system. This library has been tested on the MSP430F169 and MSP1430F149 microcontrollers and can be used...
灞波儿奔 Microcontroller MCU
Colorful interface
I made an interface using evc under wince. I want to ask how to make this interface colorful and the buttons colorful as well....
lafargefox Embedded System
Verilog HDL Issues
I recently wrote a Verilog code for driving an 8-bit common cathode digital tube. Since I am a beginner, I have many questions. The following is a parameter definition question. I have not solved it f...
落日归侠 FPGA/CPLD
I saw several ADI chips used in radio and television security matrices. They are very unique. Let me introduce them to you.
[i=s]This post was last edited by jameswangsynnex on 2015-3-3 19:58[/i]QXGA or 1080p video transmission [/size][/font][/color][/align][/align][align=left][align=left][color=#000000][font=Symbol][size=...
jameswangsynnex Mobile and portable
Timing Constraint Issues
When designing in timequest timing simulation, there will be setup time timing problems. I would like to ask, is it necessary to change the slack to positive to indicate that the project can run norma...
shuxueaw FPGA/CPLD
Should there be such an FPGA (CPLD) development board on the market?
A development board includes FPGA (CPLD) + microprocessor + USB PHY chip. It includes a USB port and several I/O ports. The USB is connected to the computer. The purpose of different I/O is set throug...
littleshrimp FPGA/CPLD

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 404  1010  2684  876  2593  9  21  55  18  53 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号