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AT27C512R-70JC

Description
IC EPROM 512K PARALLEL 32PLCC
Categorystorage   
File Size172KB,12 Pages
ManufacturerMicrochip
Websitehttps://www.microchip.com
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AT27C512R-70JC Overview

IC EPROM 512K PARALLEL 32PLCC

AT27C512R-70JC Parametric

Parameter NameAttribute value
memory typenon-volatile
memory formatEPROM
technologyEPROM - OTP
storage512Kb (64K x 8)
Write cycle time - words, pages-
interview time70ns
memory interfacein parallel
Voltage - Power4.5 V ~ 5.5 V
Operating temperature0°C ~ 70°C(TC)
Installation typesurface mount
Package/casing32-LCC (J-lead)
Supplier device packaging32-PLCC
Features
Fast Read Access Time - 45 ns
Low-Power CMOS Operation
– 100
µ
A max. Standby
– 20 mA max. Active at 5 MHz
JEDEC Standard Packages
– 28-Lead 600-mil PDIP
– 32-Lead PLCC
– 28-Lead TSOP and SOIC
5V
±
10% Supply
High-Reliability CMOS Technology
– 2,000V ESD Protection
– 200 mA Latchup Immunity
Rapid
Programming Algorithm - 100
µ
s/byte (typical)
CMOS and TTL Compatible Inputs and Outputs
Integrated Product Identification Code
Commercial, Industrial and Automotive Temperature Ranges
512K (64K x 8)
OTP EPROM
AT27C512R
Description
The AT27C512R is a low-power, high-performance 524,288-bit one-time programma-
ble read only memory (OTP EPROM) organized 64K by 8 bits. It requires only one 5V
power supply in normal read mode operation. Any byte can be accessed in less than
45 ns, eliminating the need for speed reducing WAIT states on high-performance
microprocessor systems.
Atmel’s scaled CMOS technology provides high-speed, lower active power consump-
tion, and significantly faster programming. Power consumption is typically only 8 mA
in Active Mode and less than 10
µA
in Standby.
(continued)
Pin Configurations
Pin Name
A0 to A15
O0 - O7
CE
OE/VPP
NC
Function
Addresses
Outputs
Chip Enable
Output Enable/VPP
No Connect
PDIP SOIC Top View
,
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
O0
O1
O2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
A14
A13
A8
A9
A11
OE/VPP
A10
CE
O7
O6
O5
O4
O3
512K EPROM
PLCC Top View
TSOP Top View
Type 1
A8
A9
A11
NC
OE/VPP
A10
CE
O7
O6
OE/VPP
A11
A9
A8
A13
A14
VCC
A15
A12
A7
A6
A5
A4
A3
22
23
24
25
26
27
28
1
2
3
4
5
6
7
21
20
19
18
17
16
15
14
13
12
11
10
9
8
A10
CE
O7
O6
O5
O4
O3
GND
O2
O1
O0
A0
A1
A2
A7
A12
A15
NC
VCC
A14
A13
O1
O2
GND
NC
O3
O4
O5
14
15
16
17
18
19
20
A6
A5
A4
A3
A2
A1
A0
NC
O0
5
6
7
8
9
10
11
12
13
4
3
2
1
32
31
30
29
28
27
26
25
24
23
22
21
Note:
PLCC Package Pins 1 and
17 are DON’T CONNECT.
Rev. 0015I–07/98
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