PDTB113/123/143/114EQA
series
50 V, 500 mA PNP resistor-equipped transistors
Rev. 1 — 30 March 2016
Product data sheet
1. Product profile
1.1 General description
PNP Resistor-Equipped Transistor (RET) family in a leadless ultra small DFN1010D-3
(SOT1215) Surface-Mounted Device (SMD) plastic package with visible and solderable
side pads.
Table 1.
Product overview
R1
1 k
2.2 k
4.7 k
10 k
R2
1 k
2.2 k
4.7 k
10 k
Package Nexperia NPN complement
DFN1010D-3
(SOT1215)
PDTD113EQA
PDTD123EQA
PDTD143EQA
PDTD114EQA
Type number
PDTB113EQA
PDTB123EQA
PDTB143EQA
PDTB114EQA
1.2 Features and benefits
500 mA output current capability
Built-in bias resistors
10% resistor ratio tolerance
Simplifies circuit design
Reduces component count
Reduced pick and place costs
Low package height of 0.37 mm
Suitable for Automatic Optical
Inspection (AOI) of solder joint
AEC-Q101 qualified
1.3 Applications
Digital applications
Cost saving alternative for
BC807/BC817 series in digital
applications
Controlling IC inputs
Switching loads
1.4 Quick reference data
Table 2.
Symbol
V
CEO
I
O
Quick reference data
Parameter
collector-emitter voltage
output current
Conditions
open base
Min
-
-
Typ
-
-
Max
50
500
Unit
V
mA
Nexperia
PDTB113/123/143/114EQA
50 V, 500 mA PNP resistor-equipped transistors
2. Pinning information
Table 3.
Pin
1
2
3
4
I
GND
O
O
Pinning
Symbol
Description
input (base)
GND (emitter)
output (collector)
output (collector)
2
4
3
GND
aaa-019606
Simplified outline
Graphic symbol
O
R1
1
I
R2
Transparent top view
3. Ordering information
Table 4.
Ordering information
Package
Name
PDTB113EQA
PDTB123EQA
PDTB143EQA
PDTB114EQA
DFN1010D-3
Description
plastic thermal enhanced ultra thin small outline
package; no leads; 3 terminals;
body: 1.1
1.0
0.37 mm
Version
SOT1215
Type number
PDTB113_123_143_114EQA_SER
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 1 — 30 March 2016
2 of 23
Nexperia
PDTB113/123/143/114EQA
50 V, 500 mA PNP resistor-equipped transistors
4. Marking
Table 5.
Marking codes
Marking code
00 00 01
01 01 01
01 01 11
01 10 11
Type number
PDTB113EQA
PDTB123EQA
PDTB143EQA
PDTB114EQA
4.1 Binary marking code description
READING
DIRECTION
MARKING CODE
(EXAMPLE)
YEAR DATE
CODE
VENDOR CODE
PIN 1
INDICATION MARK
MARK-FREE AREA
READING EXAMPLE:
11
01
10
aaa-008041
Fig 1.
SOT1215 binary marking code description
5. Limiting values
Table 6.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
V
CBO
V
CEO
V
EBO
Parameter
collector-base voltage
collector-emitter voltage
emitter-base voltage
Conditions
open emitter
open base
open collector
Min
-
-
-
Max
50
50
10
Unit
V
V
V
PDTB113_123_143_114EQA_SER
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 1 — 30 March 2016
3 of 23
Nexperia
PDTB113/123/143/114EQA
50 V, 500 mA PNP resistor-equipped transistors
Table 6.
Limiting values
…continued
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
V
I
Parameter
input voltage
PDTB113EQA
PDTB123EQA
PDTB143EQA
PDTB114EQA
I
O
P
tot
output current
total power dissipation
T
amb
25
C
[1]
[2]
[3]
[4]
Conditions
Min
10
12
30
50
-
-
-
-
-
-
55
65
Max
+10
+10
+10
+10
500
325
575
525
940
150
+150
+150
Unit
V
V
V
V
mA
mW
mW
mW
mW
C
C
C
T
j
T
amb
T
stg
[1]
[2]
[3]
[4]
junction temperature
ambient temperature
storage temperature
Device mounted on an FR4 Printed-Circuit Board (PCB), single-sided copper, tin-plated and standard
footprint.
Device mounted on an FR4 PCB, single-sided copper, tin-plated; mounting pad for collector 1 cm
2
.
Device mounted on an FR4 PCB, 4-layer copper, tin-plated and standard footprint.
Device mounted on an FR4 PCB, 4-layer copper, tin-plated; mounting pad for collector 1 cm
2
.
1
P
tot
(W)
0.8
(1)
aaa-020277
0.6
(2)
(3)
0.4
(4)
0.2
0
-75
-25
25
75
125
175
T
amb
(ºC)
(1) FR4 PCB, 4-layer copper, 1 cm
2
(2) FR4 PCB, single-sided copper, 1 cm
2
(3) FR4 PCB, 4-layer copper, standard footprint
(4) FR4 PCB, single sided copper, standard footprint
Fig 2.
Power derating curves
PDTB113_123_143_114EQA_SER
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 1 — 30 March 2016
4 of 23
Nexperia
PDTB113/123/143/114EQA
50 V, 500 mA PNP resistor-equipped transistors
6. Thermal characteristics
Table 7.
Symbol
R
th(j-a)
Thermal characteristics
Parameter
thermal resistance from junction
to ambient
Conditions
in free air
[1]
[2]
[3]
[4]
Min
-
-
-
-
-
Typ
-
-
-
-
-
Max
385
218
239
133
40
Unit
K/W
K/W
K/W
K/W
K/W
R
th(j-sp)
thermal resistance from junction
to solder point
[1]
[2]
[3]
[4]
Device mounted on an FR4 Printed-Circuit Board (PCB), single-sided copper, tin-plated and standard footprint.
Device mounted on an FR4 PCB, single-sided copper, tin-plated; mounting pad for collector 1 cm
2
.
Device mounted on an FR4 PCB, 4-layer copper, tin-plated and standard footprint.
Device mounted on an FR4 PCB, 4-layer copper, tin-plated; mounting pad for collector 1 cm
2
.
10
3
Z
th(j-a)
(K/W)
10
2
duty cycle = 1
0.75
0.5
0.33
0.2
0.1
0.05
10
0.02
aaa-020278
0.01
0
1
10
-5
10
-4
10
-3
10
-2
10
-1
1
10
10
2
t
p
(s)
10
3
FR4 PCB, single-sided copper, tin-plated and standard footprint.
Fig 3.
Transient thermal impedance from junction to ambient as a function of pulse duration; typical values
PDTB113_123_143_114EQA_SER
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 1 — 30 March 2016
5 of 23
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