FDS5692Z N-Channel UltraFET Trench
®
MOSFET
February 2006
FDS5692Z
N-Channel UltraFET Trench
®
MOSFET
50V, 5.8A, 24mΩ
General Description
This N-Channel UltraFET device has been designed
specifically to improve the overall efficiency of DC/DC
converters using either synchronous or conventional
switching PWM controllers. It has been optimized for
low gate charge, low r
DS
(on)
and fast switching speed.
Features
Max r
DS
(on)
= 24mΩ at V
GS
= 10V, I
D
= 5.8A
Max r
DS
(on)
= 33mΩ at V
GS
= 4.5V, I
D
= 5.6A
ESD protection diode (note 3)
Low Qgd
Fast switching speed
Applications
DC/DC converter
D
D
D
D
5
6
4
3
2
1
SO-8
S
S
S
G
7
8
MOSFET Maximum Ratings
Symbol
V
DS
V
GS
I
D
Drain-Source Voltage
Gate-Source Voltage
Drain Current – Continuous
– Pulsed
E
AS
P
D
Single Pulse Avalanche Energy
T
A
=25
o
C unless otherwise noted
Parameter
Ratings
50
±
20
(Note 1a)
Units
V
V
A
5.8
40
72
mJ
W
UltraFET Dissipation for Single Operation
(Note 1a)
(Note 1b)
(Note 1c)
2.5
1.2
1.1
–55 to 150
T
J
, T
STG
Operating and Storage Junction Temperature Range
°C
Thermal Characteristics
R
θJA
R
θJA
R
θJC
Thermal Resistance, Junction-to-Ambient
Thermal Resistance, Junction-to-Ambient
Thermal Resistance, Junction-to-Case
(Note 1a)
(Note 1c)
(Note 1)
50
125
25
°C/W
Package Marking and Ordering Information
Device Marking
FDS5692Z
©2006
Fairchild Semiconductor Corporation
FDS5692Z Rev C(W)
Device
FDS5692Z
Package
SO-8
Reel Size
13”
Tape width
12mm
Quantity
2500units
www.fairchildsemi.com
FDS5692Z N-Channel UltraFET Trench
®
MOSFET
Electrical Characteristics
Symbol
Parameter
Drain-Source Avalanche Energy
(Single Pulse)
Drain-Source Avalanche Current
T
A
= 25°C unless otherwise noted
Test Conditions
Min
Typ
Max Units
Drain-Source Avalanche Ratings
E
AS
I
AS
V
DD
= 50 V, I
D
= 12 A, L=1mH
12
I
D
= 250
μA
72
mJ
A
Off Characteristics
BV
DSS
ΔBV
DSS
ΔT
J
I
DSS
I
GSS
Drain–Source Breakdown Voltage
Breakdown Voltage Temperature
Coefficient
Zero Gate Voltage Drain Current
Gate–Body Leakage
(Note 4)
V
GS
= 0 V,
50
48
1
±
10
V
mV/°C
μA
μA
I
D
= 250
μA,
Referenced to 25°C
V
DS
= 40 V
V
GS
=
±
20V,
V
GS
= 0 V
V
DS
= 0 V
On Characteristics
V
GS(th)
ΔV
GS(th)
ΔT
J
r
DS
(on)
Gate Threshold Voltage
Gate Threshold Voltage
Temperature Coefficient
Static Drain–Source
On–Resistance
V
DS
= V
GS
,
I
D
= 250
μA
I
D
= 250
μA,
Referenced to 25°C
I
D
= 5.8 A
V
GS
= 10 V,
I
D
= 5.6 A
V
GS
= 4.5 V,
V
GS
= 10 V, I
D
= 5.8A, T
J
= 125°C
1
1.6
–6
20
26
32
3
V
mV/°C
24
33
41
mΩ
Dynamic Characteristics
C
iss
C
oss
C
rss
R
G
Q
g(TOT)
Q
g(TOT)
Q
gs
Q
gd
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Gate Resistance
Total Gate Charge, V
GS
= 10V
Total Gate Charge, V
GS
= 5V
Gate–Source Gate Charge
Gate–Drain Gate Charge
(Note 4)
V
DS
= 25 V,
f = 1.0 MHz
f = 1.0 MHz
V
DS
= 25V,
V
GS
= 0 V,
1025
150
50
0.79
18
25
14
pF
pF
pF
Ω
nC
nC
nC
nC
I
D
= 5.8A
10
2.8
3.0
Switching Characteristics
t
d(on)
t
r
t
d(off)
t
f
Turn–On Delay Time
Rise Time
Turn–Off Delay Time
Fall Time
V
DD
= 25 V,
V
GS
= 10 V,
I
D
= 5.8A,
R
GEN
= 6
Ω
9
5
27
6
18
10
43
12
ns
ns
ns
ns
FDS5692Z Rev C(W)
www.fairchildsemi.com
FDS5692Z N-Channel UltraFET Trench
®
MOSFET
Electrical Characteristics
Symbol
V
SD
t
rr
Q
rr
T
A
= 25°C unless otherwise noted
Parameter
Drain–Source Diode Forward
Voltage
Reverse Recovery Time
Reverse Recovery Charge
Test Conditions
I
S
= 5.8 A
I
S
= 2.9 A
dI
F
/dt = 100A/μs
Min
Typ
0.79
0.75
24
16
Max Units
1.25
1.0
V
V
ns
nC
Drain–Source Diode Characteristics
V
GS
= 0 V,
I
F
= 6A,
Notes:
1.
R
θJA
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of
the drain pins. R
θJC
is guaranteed by design while R
θCA
is determined by the user's board design.
a) 50°C/W when
2
mounted on a 1in
pad of 2 oz copper
b) 105°C/W when
2
mounted on a .04 in
pad of 2 oz copper
c) 125°C/W when mounted on a
minimum pad.
Scale 1 : 1 on letter size paper
2.
Pulse Test: Pulse Width < 300μs, Duty Cycle < 2.0%
3.
The diode connected between the gate and source serves only as protection against ESD. No gate overvoltage rating is implied.
FDS5692Z Rev C(W)
www.fairchildsemi.com
FDS5692Z N-Channel UltraFET Trench
®
MOSFET
Typical Characteristics
40
V
GS
= 10V
4.5V
4.0V
NORMALIZED
DRAIN-SOURCE ON-RESISTANCE
2.4
V
GS
= 3.0V
2.2
2
1.8
3.5V
1.6
4.0V
1.4
1.2
10V
1
0.8
4.5V
5.0V
6.0V
I
D
, DRAIN CURRENT (A)
32
6.0V
24
3.5.V
16
3.0V
8
2.5V
0
0
1
2
3
V
DS
, DRAIN-SOURCE VOLTAGE (V)
4
0
10
20
I
D
, DRAIN CURRENT (A)
30
40
Figure 1. On-Region Characteristics.
Figure 2. On-Resistance Variation with
Drain Current and Gate Voltage.
0.09
r
DS
(on)
, ON-RESISTANCE (OHM)
2
NORMALIZED
DRAIN-SOURCE ON-RESISTANCE
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
-50
I
D
= 5.8A
V
GS
= 5V
I
D
= 2.9A
0.07
0.05
T
A
= 125 C
o
0.03
T
A
= 25 C
o
0.01
-25
0
25
50
75
100
o
125
150
2
T
J
, JUNCTION TEMPERATURE ( C)
4
6
8
V
GS
, GATE TO SOURCE VOLTAGE (V)
10
Figure 3. On-Resistance Variation with
Temperature.
40
V
DS
= 5V
T
A
= -55 C
o
Figure 4. On-Resistance Variation with
Gate-to-Source Voltage.
100
125 C
o
I
S
, REVERSE DRAIN CURRENT (A)
V
GS
= 0V
10
T
A
= 125
o
C
1
25
o
C
0.1
-55
o
C
I
D
, DRAIN CURRENT (A)
30
25 C
o
20
0.01
10
0.001
0
0
1
2
3
4
V
GS
, GATE TO SOURCE VOLTAGE (V)
5
0.0001
0
0.2
0.4
0.6
0.8
1
1.2
V
SD
, BODY DIODE FORWARD VOLTAGE (V)
Figure 5. Transfer Characteristics.
Figure 6. Body Diode Forward Voltage Variation
with Source Current and Temperature.
FDS5692Z Rev C(W)
www.fairchildsemi.com
FDS5692Z N-Channel UltraFET Trench
®
MOSFET
Typical Characteristics
10
1500
I
D
= 5.8A
f = 1MHz
V
GS
= 0 V
1200
V
DS
= 20V
30V
V
GS
, GATE-SOURCE VOLTAGE (V)
8
6
25V
4
CAPACITANCE (pF)
900
C
iss
600
C
oss
300
C
rss
2
0
0
4
8
12
16
20
0
0
5
10
15
20
25
30
Q
g
, GATE CHARGE (nC)
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
Figure 7. Gate Charge Characteristics.
100
P(pk), PEAK TRANSIENT POWER (W)
100µs
1ms
10ms
100ms
1s
10s
DC
V
GS
= 10V
SINGLE PULSE
o
R
θ
JA
= 125 C/W
T
A
= 25
o
C
40
Figure 8. Capacitance Characteristics.
R
DS(ON)
LIMIT
I
D
, DRAIN CURRENT (A)
10
30
SINGLE PULSE
R
θ
JA
= 125°C/W
T
A
= 25°C
1
20
0.1
10
0.01
0.01
0.1
1
10
V
DS
, DRAIN-SOURCE VOLTAGE (V)
100
0
0.001
0.01
0.1
1
t
1
, TIME (sec)
10
100
Figure 9. Maximum Safe Operating Area.
Figure 10. Single Pulse Maximum
UltraFET Dissipation.
r(t), NORMALIZED EFFECTIVE
TRANSIENT THERMAL RESISTANCE
1
D = 0.5
0.2
R
θJA
(t) = r(t) * R
θJA
R
θJA
= 125 °C/W
0.1
0.1
0.05
0.02
P(pk)
t
1
t
2
T
J
- T
A
= P * R
θJA
(t)
Duty Cycle, D = t
1
/ t
2
0.01
0.01
SINGLE PULSE
0.001
0.0001
0.001
0.01
0.1
t
1
, TIME (sec)
1
10
100
1000
Figure 11. Transient Thermal Response Curve.
Thermal characterization performed using the conditions described in Note 1c.
Transient thermal response will change depending on the circuit board design.
FDS5692Z Rev C(W)
www.fairchildsemi.com
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