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SY88927VZCTR

Description
5V/3.3V 2.5Gbps HIGH-SPEED DIFFERENTIAL RECEIVER
CategoryAnalog mixed-signal IC    Drivers and interfaces   
File Size67KB,5 Pages
ManufacturerMicrochip
Websitehttps://www.microchip.com
Download Datasheet Parametric View All

SY88927VZCTR Overview

5V/3.3V 2.5Gbps HIGH-SPEED DIFFERENTIAL RECEIVER

SY88927VZCTR Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerMicrochip
Parts packaging codeSOIC
package instruction3 MM, MSOP-8
Contacts8
Reach Compliance Code_compli
ECCN codeEAR99
Input propertiesDIFFERENTIAL
Interface integrated circuit typeLINE RECEIVER
JESD-30 codeR-PDSO-G8
Nominal negative supply voltage-3.3 V
Number of functions1
Number of terminals8
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Package body materialPLASTIC/EPOXY
encapsulated codeSOP
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Certification statusNot Qualified
Maximum receive delay0.36 ns
Number of receiver bits1
surface mountYES
technologyECL
Temperature levelINDUSTRIAL
Terminal formGULL WING
Terminal locationDUAL
5V/3.3V 2.5Gbps
HIGH-SPEED
DIFFERENTIAL RECEIVER
FEATURES
s
3.3V and 5V power supply options
s
Maximum frequency > 3.0GHz
s
Internal 75K
input pull-down resistors
s
Faster version of SY100EL16V
s
100K ECL compatible I/O
s
Improved output waveform characteristics
s
Available in 8-pin (3mm) MSOP and SOIC package
SY88927V
DESCRIPTION
The SY88927V is a 2.5Gbps high-speed differential
receiver. The device is functionally equivalent to the
EL16V devices, with higher performance capabilities. With
output transition times significantly faster than the EL16V,
the SY88927V is ideally suited for interfacing with high-
frequency sources.
The SY88927V provides a V
BB
output for either single-
ended use or as a DC bias for AC coupling to the device.
The V
BB
pin should be used only as a bias for the
SY88927V as its current sink/source capability is limited.
Whenever used, the V
BB
pin should be bypassed to
ground via a 0.01µF capacitor.
Under open input conditions (pulled to V
EE
), internal
input clamps will force the Q output LOW.
PIN CONFIGURATION/BLOCK DIAGRAM
PIN NAMES
Pin
D
Data Inputs
Data Outputs
Reference Voltage Output
Function
NC 1
D 2
/D 3
V
BB
4
8 V
CC
7 Q
6 /Q
5 V
EE
Q
V
BB
(Available in MSOP or SOIC packages)
Rev.: C
Amendment: /0
1
Issue Date: July 2000
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