SY10E160JZ datasheet, PDF - EEWORLD Datasheet

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SY10E160JZ: Description12-BIT PARITY GENERATOR/CHECKER; Categorylogic logic; File Size60KB，5 Pages; ManufacturerMicrochip; Websitehttps://www.microchip.com; Environmental Compliance

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SY10E160JZ Overview

12-BIT PARITY GENERATOR/CHECKER

SY10E160JZ Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Microchip
Parts packaging code	QLCC
package instruction	QCCJ,
Contacts	28
Reach Compliance Code	compli
series	10E
JESD-30 code	S-PQCC-J28
JESD-609 code	e3
length	11.48 mm
Logic integrated circuit type	PARITY GENERATOR/CHECKER
Humidity sensitivity level	2
Number of digits	12
Number of functions	1
Number of terminals	28
Maximum operating temperature	85 °C
Minimum operating temperature
Output polarity	COMPLEMENTARY
Package body material	PLASTIC/EPOXY
encapsulated code	QCCJ
Package shape	SQUARE
Package form	CHIP CARRIER
Peak Reflow Temperature (Celsius)	260
propagation delay (tpd)	0.95 ns
Certification status	Not Qualified
Maximum seat height	4.57 mm
surface mount	YES
technology	ECL
Temperature level	COMMERCIAL EXTENDED
Terminal surface	Matte Tin (Sn)
Terminal form	J BEND
Terminal pitch	1.27 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED
width	11.48 mm

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Micrel, Inc.

12-BIT PARITY

GENERATOR/CHECKER

SY10E160

SY100E160

SY10E160

SY100E160

FEATURES

Provides odd-HIGH parity of 12 inputs

Extended 100E V

range of –4.2V to –5.5V

Output register with Shift/Hold capability

900ps max. D to Q, /Q output

Enable control

Asynchronous Register Reset

DESCRIPTION

The SY10/100E160 are high-speed, 12-bit parity

generator/checkers with differential outputs, for use in

new, high-performance ECL systems. The output Q takes

on a logic HIGH value only when an odd number of inputs

are at a logic HIGH. A logic HIGH on the enable input (EN)

forces the output Q to a logic LOW.

An additional feature of the E160 is the output register.

Two multiplexers and their associated signals control the

data, loading the new parity data or shifting external data

in. To hold the present data, the Hold signal (HOLD) must

be at a logic LOW level. If the HOLD signal is at a logic

HIGH, the data present at the Q output is passed through

the first multiplexer. Taking the Shift signal (SHIFT) to a

logic HIGH will shift the data at the S-IN pin into the output

of the first multiplexer is then passed through to the register.

The register itself is clocked on the rising edge of CLK

or CLK

(or both). The presence of a logic HIGH on the

reset pin (R) forces the register output Y to a logic LOW.

Differential outputs

Fully compatible with industry standard 10KH,

100K ECL levels

Internal 75K

Ω

input pulldown resistors

Fully compatible with Motorola MC10E/100E160

Available in 28-pin PLCC package

BLOCK DIAGRAM

HOLD

S-IN

SHIFT

CLK

MUX

SEL

MUX

M9999-032006

hbwhelp@micrel.com or (408) 955-1690

Rev.: F

Amendment: /0

Issue Date: March 2006

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Shortcut: S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 SA SB SC SD SE SF SG SH SI SJ SK SL SM SN SO SP SQ SR SS ST SU SV SW SX SY SZ T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 TA TB TC TD TE TF TG TH TI TJ TK TL TM TN TO TP TQ TR TS TT TU TV TW TX TY TZ U0 U1 U2 U3 U4 U6 U7 U8 UA UB UC UD UE UF UG UH UI UJ UK UL UM UN UP UQ UR US UT UU UV UW UX UZ V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 VA VB VC VD VE VF VG VH VI VJ VK VL VM VN VO VP VQ VR VS VT VU VV VW VX VY VZ W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 WA WB WC WD WE WF WG WH WI WJ WK WL WM WN WO WP WR WS WT WU WV WW WY X0 X1 X2 X3 X4 X5 X7 X8 X9 XA XB XC XD XE XF XG XH XK XL XM XN XO XP XQ XR XS XT XU XV XW XX XY XZ Y0 Y1 Y2 Y4 Y5 Y6 Y9 YA YB YC YD YE YF YG YH YK YL YM YN YP YQ YR YS YT YX Z0 Z1 Z2 Z3 Z4 Z5 Z6 Z8 ZA ZB ZC ZD ZE ZF ZG ZH ZJ ZL ZM ZN ZP ZR ZS ZT ZU ZV ZW ZX ZY

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