SY10E156 datasheet, PDF - EEWORLD Datasheet

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SY10E156: Description3-BIT 4:1 MUX-LATCH; File Size63KB，4 Pages; ManufacturerMicrochip; Websitehttps://www.microchip.com

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SY10E156 Overview

3-BIT 4:1 MUX-LATCH

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3-BIT 4:1

MUX-LATCH

SY10E156

SY100E156

FINAL

FEATURES

900ps max. D to output

Extended 100E V

range of –4.2V to –5.5V

800ps max. LEN to output

Differential outputs

Asynchronous Master Reset

Dual latch enables

DESCRIPTION

The SY10/100E156 offer three 4:1 multiplexers followed

by latches with differential outputs, designed for use in

new, high-performance ECL systems. The two external

latch enable signals (LEN

and LEN

) are gated through a

logical OR operation before use as control for the three

latches. When both LEN

and LEN

are at a logic LOW, the

latches are transparent, thus presenting the data from the

multiplexers at the output pins. If either LEN

or LEN

(or

both) are at a logic HIGH, the outputs are latched.

The multiplexer operation is controlled by the Select

(SEL

, SEL

) signals which select one of the four bits of

input data at each mux to be passed through.

The MR (Master Reset) signal operates asynchronously

to take all outputs to a logic LOW.

Fully compatible with industry standard 10KH,

100K ECL levels

Internal 75K

Ω

input pulldown resistors

Fully compatible with Motorola MC10E/100E156

Available in 28-pin PLCC package

BLOCK DIAGRAM

PIN CONFIGURATION

CCO

4:1

MUX

N R

SEL

25 24 23 22 21 20 19

CCO

4:1

MUX

N R

LEN

PLCC

TOP VIEW

J28-1

10 11

SEL

LEN

4:1

MUX

N R

PIN NAMES

–D

SEL

, SEL

LEN

, LEN

–Q

CCO

Function

Input Data

Select Inputs

Latch Enables

Master Reset

True Outputs

Inverted Outputs

to Output

Rev.: C

Amendment: /1

CCO

Issue Date: February, 1998

SY10E156 Related Products

	SY10E156	SY100E156JCTR	SY100E156JC	SY100E156	SY10E156JC	SY10E156JCTR
Description	3-BIT 4:1 MUX-LATCH	3-BIT 4:1 MUX-LATCH	3-BIT 4:1 MUX-LATCH	3-BIT 4:1 MUX-LATCH	3-BIT 4:1 MUX-LATCH	3-BIT 4:1 MUX-LATCH

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