FDZ209N
May 2004
FDZ209N
60V N-Channel PowerTrench BGA MOSFET
General Description
Combining Fairchild’s advanced PowerTrench process
with state-of-the-art BGA packaging, the FDZ209N
minimizes both PCB space and R
DS(ON)
. This BGA
MOSFET embodies a breakthrough in packaging
technology which enables the device to combine
excellent thermal transfer characteristics, high current
handling capability, ultra-low profile packaging, low gate
charge, and low R
DS(ON)
.
Features
•
4 A, 60 V.
R
DS(ON)
= 80 mΩ @ V
GS
= 5 V
•
Occupies only 5 mm
2
of PCB area: only 55% of the
area of SSOT-6
•
Ultra-thin package: less than 0.80 mm height when
mounted to PCB
•
Outstanding thermal transfer characteristics:
4 times better than SSOT-6
•
Ultra-low Q
g
x R
DS(ON)
figure-of-merit
•
High power and current handling capability
Applications
•
Solenoid Drivers
D
S
D
S
S
D
D
S
S
D
D
Index
slot
Index
slot
G
D
G
Bottom
Top
T
A
=25
o
C unless otherwise noted
S
Absolute Maximum Ratings
V
DSS
V
GSS
I
D
Symbol
P
D
T
J
, T
STG
Drain-Source Voltage
Gate-Source Voltage
Drain Current – Continuous
(Note 1a)
– Pulsed
Power Dissipation (Steady State)
(Note 1a)
Operating and Storage Junction Temperature Range
Parameter
60
±20
4
20
2
–55 to +150
Ratings
Units
V
V
A
W
°C
Thermal Characteristics
R
θ
JA
R
θ
JB
R
θ
JC
Thermal Resistance, Junction-to-Ambient
Thermal Resistance, Junction-to-Ball
Thermal Resistance, Junction-to-Case
(Note 1a)
(Note 1)
(Note 1)
64
8
0.7
°C/W
Package Marking and Ordering Information
Device Marking
209N
Device
FDZ209N
Reel Size
7’’
Tape width
8mm
Quantity
3000 units
©
2004 Fairchild Semiconductor Corporation
FDZ209N Rev B2 (W)
FDZ209N
Electrical Characteristics
Symbol
W
DSS
I
AR
BV
DSS
∆BV
DSS
∆T
J
I
DSS
I
GSS
V
GS(th)
∆V
GS(th)
∆T
J
R
DS(on)
g
FS
C
iss
C
oss
C
rss
R
G
t
d(on)
t
r
t
d(off)
t
f
Q
g
Q
gs
Q
gd
I
S
V
SD
t
rr
Q
rr
T
A
= 25° unless otherwise noted
C
Parameter
Drain-Source Avalanche Energy
Drain-Source Avalanche Current
Drain–Source Breakdown Voltage
Breakdown Voltage Temperature
Coefficient
Zero Gate Voltage Drain Current
Gate–Body Leakage.
(Note 2)
Test Conditions
Single Pulse,
I
D
= 4 A
V
GS
= 0 V,
I
D
= 250
µA
I
D
= 250
µA,
Referenced to 25°C
V
DS
= 48 V,
V
GS
=
±20
V,
V
GS
= 0 V
V
DS
= 0 V
V
DD
= 30 V,
Min
Typ
Max Units
90
4
mJ
A
V
mV/°C
1
±100
µA
nA
V
mV/°C
mΩ
S
pF
pF
pF
Ω
32
8
27
16
9
ns
ns
ns
ns
nC
nC
nC
1.7
1.2
A
V
nS
nC
Drain-Source Avalanche Ratings
(Note 2)
Off Characteristics
60
59
On Characteristics
Gate Threshold Voltage
Gate Threshold Voltage
Temperature Coefficient
Static Drain–Source
On–Resistance
Forward Transconductance
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Gate Resistance
(Note 2)
V
DS
= V
GS
,
I
D
= 250
µA
I
D
= 250
µA,
Referenced to 25°C
V
GS
= 5 V,
I
D
= 4 A
V
GS
= 5 V, I
D
= 4 A, T
J
=125°C
V
DS
= 5 V,
I
D
= 4 A
V
DS
= 30 V,
f = 1.0 MHz
V
GS
= 15 mV,
V
DD
= 30 V,
V
GS
= 5 V,
V
GS
= 0 V,
1
2.5
–6
60
91
12
657
76
32
3
80
130
Dynamic Characteristics
f = 1.0 MHz
I
D
= 1 A,
R
GEN
= 6
Ω
1.5
18
4
15
8
Switching Characteristics
Turn–On Delay Time
Turn–On Rise Time
Turn–Off Delay Time
Turn–Off Fall Time
Total Gate Charge
Gate–Source Charge
Gate–Drain Charge
V
DS
= 30 V,
V
GS
= 5 V
I
D
= 4 A,
6.3
2.5
2.5
Drain–Source Diode Characteristics and Maximum Ratings
Maximum Continuous Drain–Source Diode Forward Current
Drain–Source Diode Forward
V
GS
= 0 V, I
S
= 1.7 A
Voltage
Diode Reverse Recovery Time
I
F
= 4A
d
iF
/d
t
= 100 A/µs
Diode Reverse Recovery Charge
(Note 2)
0.77
27
(Note 2)
45
Notes:
1.
R
θ
JA
is determined with the device mounted on a 1 in² 2 oz. copper pad on a 1.5 x 1.5 in. board of FR-4 material. The thermal resistance from the junction to
copper chip carrier. R
θ
JC
and R
θ
JB
are guaranteed by design while R
θ
JA
is determined by the user' board design.
s
the circuit board side of the solder ball, R
θ
JB
, is defined for reference. For R
θ
JC
, the thermal reference point for the case is defined as the top surface of the
a)
64°
C/W when
mounted on a 1in
2
pad
of 2 oz copper, 1.5” x
1.5” x 0.062” thick
PCB
b)
128°
C/W when mounted
on a minimum pad of 2 oz
copper
Scale 1 : 1 on letter size paper
2.
Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%
FDZ209N Rev B2 (W)
Dimensional Outline and Pad Layout
FDZ209N
FDZ209N Rev B2 (W)
FDZ209N
Typical Characteristics
20
R
DS(ON)
, NORMALIZED
DRAIN-SOURCE ON-RESISTANCE
V
GS
= 5.0V
1.8
4.8V
4.5V
I
D
, DRAIN CURRENT (A)
15
1.6
V
GS
= 4.0V
1.4
4.3V
10
4.3V
1.2
4.5V
4.8V
5.0V
4.0V
5
3.8V
1
0
0
1
2
3
4
5
6
7
V
DS
, DRAIN-SOURCE VOLTAGE (V)
0.8
0
5
10
I
D
, DRAIN CURRENT (A)
15
20
Figure 1. On-Region Characteristics.
Figure 2. On-Resistance Variation with
Drain Current and Gate Voltage.
0.35
R
DS(ON)
, ON-RESISTANCE (OHM)
I
D
=2A
0.3
0.25
0.2
0.15
0.1
0.05
0
3
3.5
4
4.5
5
V
GS
, GATE TO SOURCE VOLTAGE (V)
T
A
= 25
o
C
T
A
= 125
o
C
1.8
R
DS(ON)
, NORMALIZED
DRAIN-SOURCE ON-RESISTANCE
1.6
1.4
1.2
1
0.8
0.6
0.4
-50
-25
0
25
50
75
100
o
I
D
= 4A
V
GS
= 5.0V
125
150
T
J
, JUNCTION TEMPERATURE ( C)
Figure 3. On-Resistance Variation with
Temperature.
20
V
DS
= 5V
I
D
, DRAIN CURRENT (A)
15
T
A
= -55 C
o
Figure 4. On-Resistance Variation with
Gate-to-Source Voltage.
100
V
GS
= 0V
T
A
= 125
o
C
1
0.1
0.01
-55
o
C
0.001
0.0001
25 C
o
I
S
, REVERSE DRAIN CURRENT (A)
10
125 C
o
10
25
o
C
5
0
2
2.5
3
3.5
4
4.5
5
5.5
V
GS
, GATE TO SOURCE VOLTAGE (V)
0
0.2
0.4
0.6
0.8
1
1.2
V
SD
, BODY DIODE FORWARD VOLTAGE (V)
Figure 5. Transfer Characteristics.
Figure 6. Body Diode Forward Voltage Variation
with Source Current and Temperature.
FDZ209N Rev B2 (W)
FDZ209N
Typical Characteristics
7
V
GS
, GATE-SOURCE VOLTAGE (V)
6
I
D
= 4A
V
DS
= 20V
40V
30V
1000
f = 1MHz
V
GS
= 0 V
C
ISS
800
CAPACITANCE (pF)
5
4
3
2
1
0
0
2
4
6
600
400
C
OSS
200
C
RSS
8
10
0
0
10
20
30
40
50
60
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
Q
g
, GATE CHARGE (nC)
Figure 7. Gate Charge Characteristics.
100
Figure 8. Capacitance Characteristics.
50
1ms
I
D
, DRAIN CURRENT (A)
10
100ms
1
V
GS
= 5.0V
SINGLE PULSE
R
θJA
= 128
o
C/W
T
A
= 25 C
0.01
0.1
1
10
100
V
DS
, DRAIN-SOURCE VOLTAGE (V)
o
P(pk), PEAK TRANSIENT POWER (W)
R
DS(ON)
LIMIT
40
10ms
SINGLE PULSE
R
θJA
= 128°
C/W
T
A
= 25°
C
30
DC
1s
10s
20
0.1
10
0
0.01
0.1
1
10
100
1000
t
1
, TIME (sec)
Figure 9. Maximum Safe Operating Area.
Figure 10. Single Pulse Maximum
Power Dissipation.
r(t), NORMALIZED EFFECTIVE TRANSIENT
THERMAL RESISTANCE
1
D = 0.5
0.2
R
θJA
(t) = r(t) * R
θJA
R
θJA
= 128 °
C/W
P(pk)
t
2
T
J
- T
A
= P * R
θJA
(t)
Duty Cycle, D = t
1
/ t
2
SINGLE PULSE
0.1
0.1
0.05
0.02
t
1
0.01
0.01
0.001
0.001
0.01
0.1
1
t
1
, TIME (sec)
10
100
1000
Figure 11. Transient Thermal Response Curve.
Thermal characterization performed using the conditions described in Note 1b.
Transient thermal response will change depending on the circuit board design.
FDZ209N Rev B2 (W)
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