SY100EL38LZGTR datasheet, PDF - EEWORLD Datasheet

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SY100EL38LZGTR: Description5V/3.3V ±2, ±4/6 CLOCK GENERATION CHIP; Categorylogic logic; File Size97KB，6 Pages; ManufacturerMicrochip; Websitehttps://www.microchip.com; Environmental Compliance

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SY100EL38LZGTR Overview

5V/3.3V ±2, ±4/6 CLOCK GENERATION CHIP

SY100EL38LZGTR Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Microchip
Parts packaging code	SOIC
package instruction	SOP,
Contacts	20
Reach Compliance Code	compli
series	100EL
Input adjustment	DIFFERENTIAL
JESD-30 code	R-PDSO-G20
JESD-609 code	e4
length	12.83 mm
Logic integrated circuit type	LOW SKEW CLOCK DRIVER
Humidity sensitivity level	2
Number of functions	1
Number of inverted outputs
Number of terminals	20
Actual output times	4
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Peak Reflow Temperature (Celsius)	260
propagation delay (tpd)	1.22 ns
Certification status	Not Qualified
Same Edge Skew-Max（tskwd）	0.075 ns
Maximum seat height	2.65 mm
surface mount	YES
technology	ECL
Temperature level	INDUSTRIAL
Terminal surface	NICKEL PALLADIUM GOLD
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	7.52 mm
minfmax	1000 MHz

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NOT RECOMMENDED FOR NEW DESIGNS

Micrel, Inc.

5V/3.3V

4/6 CLOCK

GENERATION CHIP

Precision Edge

SY10EL38/L

Precision Edge

SY100EL38/L

SY10EL38/L

SY100EL38/L

FEATURES

3.3V and 5V power supply options

50ps output-to-output skew

Synchronous enable/disable

Master Reset for synchronization

Internal 75K

Ω

input pull-down resistors

Precision Edge

DESCRIPTION

The SY10/100EL38/L are low skew

÷2, ÷4/6

clock

generation chips designed explicitly for low skew clock

generation applications. The internal dividers are

synchronous to each other, therefore, the common output

edges are all precisely aligned. The devices can be driven

by either a differential or single-ended ECL or, if positive

power supplies are used, PECL input signal. In addition,

by using the V

output, a sinusoidal source can be AC-

coupled into the device. If a single-ended input is to be

used, the V

output should be connected to the CLK

input and bypassed to ground via a 0.01µF capacitor.

The V

output is designed to act as the switching

reference for the input of the EL38/L under single-ended

input conditions. As a result, this pin can only source/

sink up to 0.5mA of current.

The common enable (EN) is synchronous so that the

internal dividers will only be enabled/disabled when the

internal clock is already in the LOW state. This avoids

any chance of generating a runt clock pulse on the

internal clock when the device is enabled/disabled as

can happen with an asynchronous control. An internal

runt pulse could lead to losing synchronization between

the internal divider stages. The internal enable flip-flop is

clocked on the falling edge of the input clock, therefore,

all associated specification limits are referenced to the

negative edge of the clock input.

The Phase_Out output will go HIGH for one clock cycle

whenever the

÷2

and the

÷4/6

outputs are both

transitioning from a LOW to a HIGH. This output allows

for clock synchronization within the system.

Upon start-up, the internal flip-flops will attain a

random state; the master reset (MR) input allows for the

synchronization of the internal dividers, as well as for

multiple EL38/Ls in a system.

Available in 20-pin SOIC package

Precision Edge is a registered trademark of Micrel, Inc.

M9999-031006

hbwhelp@micrel.com or (408) 955-1690

Rev.: G

Amendment: /0

Issue Date: March 2006

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