SY100EL12ZCTR datasheet, PDF - EEWORLD Datasheet

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SY100EL12ZCTR: Description100EL SERIES, 2-INPUT OR/NOR GATE, PDSO8; Categorylogic logic; File Size47KB，4 Pages; ManufacturerMicrochip; Websitehttps://www.microchip.com

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SY100EL12ZCTR Overview

100EL SERIES, 2-INPUT OR/NOR GATE, PDSO8

SY100EL12ZCTR Parametric

Parameter Name	Attribute value
Maker	Microchip
package instruction	SOIC-8
Reach Compliance Code	compli
series	100EL
JESD-30 code	R-PDSO-G8
length	4.93 mm
Logic integrated circuit type	OR/NOR GATE
Number of functions	1
Number of entries	2
Number of terminals	8
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
propagation delay (tpd)	0.45 ns
Maximum seat height	1.73 mm
surface mount	YES
technology	ECL
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
width	3.94 mm

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LOW-IMPEDANCE

DRIVER

SY10EL12

SY100EL12

FEATURES

290ps propagation delay

Dual outputs for 25

Ω

drive applications

Internal 75K

Ω

input pull-down resistors

Available in 8-pin SOIC package

DESCRIPTION

The SY10/100EL12 are low-impedance drive buffers.

With two pairs of OR/NOR outputs, the devices are ideally

suited for high drive applications such as memory

addressing. These devices are functionally equivalent to

the E112 devices, with higher performance capabilities.

With propagation delays significantly faster than the E112,

the EL12 is ideally suited for those applications which

require the ultimate in AC performance.

PIN CONFIGURATION/BLOCK DIAGRAM

PIN NAMES

Function

Data Inputs

Data Outputs

, D

, Q

SOIC

TOP VIEW

Rev.: E

Amendment: /0

Issue Date: August, 1998

SY100EL12ZCTR Related Products

	SY100EL12ZCTR	SY10EL12	SY10EL12ZC	SY10EL12ZCTR	SY100EL12ZC
Description	100EL SERIES, 2-INPUT OR/NOR GATE, PDSO8	100EL SERIES, 2-INPUT OR/NOR GATE, PDSO8	100EL SERIES, 2-INPUT OR/NOR GATE, PDSO8	100EL SERIES, 2-INPUT OR/NOR GATE, PDSO8	100EL SERIES, 2-INPUT OR/NOR GATE, PDSO8
series	100EL	100EL	10EL	10EL	100EL
Number of functions	1	1	1	1	1
Number of terminals	8	8	8	8	8
surface mount	YES	Yes	YES	YES	YES
Terminal form	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING
Terminal location	DUAL	DUAL	DUAL	DUAL	DUAL
Maker	Microchip	-	Microchip	Microchip	Microchip
package instruction	SOIC-8	-	SOIC-8	SOIC-8	SOIC-8
Reach Compliance Code	compli	-	compli	compli	compli
JESD-30 code	R-PDSO-G8	-	R-PDSO-G8	R-PDSO-G8	R-PDSO-G8
length	4.93 mm	-	4.93 mm	4.93 mm	4.93 mm
Logic integrated circuit type	OR/NOR GATE	-	OR/NOR GATE	OR/NOR GATE	OR/NOR GATE
Number of entries	2	-	2	2	2
Package body material	PLASTIC/EPOXY	-	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	SOP	-	SOP	SOP	SOP
Package shape	RECTANGULAR	-	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE	-	SMALL OUTLINE	SMALL OUTLINE	SMALL OUTLINE
propagation delay (tpd)	0.45 ns	-	0.45 ns	0.45 ns	0.45 ns
Maximum seat height	1.73 mm	-	1.73 mm	1.73 mm	1.73 mm
technology	ECL	-	ECL	ECL	ECL
Terminal pitch	1.27 mm	-	1.27 mm	1.27 mm	1.27 mm
width	3.94 mm	-	3.94 mm	3.94 mm	3.94 mm

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Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

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