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SY100E196JYTR

Description
PROGRAMMABLE DELAY CHIP WITH ANALOG INPUT
Categorylogic    logic   
File Size110KB,10 Pages
ManufacturerMicrochip
Websitehttps://www.microchip.com
Environmental Compliance
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SY100E196JYTR Overview

PROGRAMMABLE DELAY CHIP WITH ANALOG INPUT

SY100E196JYTR Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
Parts packaging codeQLCC
package instructionQCCJ,
Contacts28
Reach Compliance Codecompli
Is SamacsysN
series100E
JESD-30 codeS-PQCC-J28
JESD-609 codee3
length11.48 mm
Logic integrated circuit typeSILICON DELAY LINE
Humidity sensitivity level2
Number of functions1
Number of taps/steps127
Number of terminals28
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Output polarityCOMPLEMENTARY
Package body materialPLASTIC/EPOXY
encapsulated codeQCCJ
Package shapeSQUARE
Package formCHIP CARRIER
Peak Reflow Temperature (Celsius)260
programmable delay lineYES
Certification statusNot Qualified
Maximum seat height4.57 mm
surface mountYES
technologyECL
Temperature levelINDUSTRIAL
Terminal surfaceMATTE TIN
Terminal formJ BEND
Terminal pitch1.27 mm
Terminal locationQUAD
Maximum time at peak reflow temperature40
Total delay nominal (td)3.63 ns
width11.48 mm
Base Number Matches1
NOT RECOMMENDED FOR NEW DESIGNS
Micrel, Inc.
PROGRAMMABLE DELAY
CHIP WITH ANALOG INPUT
Precision Edge
®
SY10E196
Precision
SY100E196
Edge
®
SY10E196
SY100E196
FEATURES
s
Up to 2ns delay range
s
Extended 100E V
EE
range of –4.2V to –5.5V
s
s
s
s
DESCRIPTION
The SY10/100E196 are programmable delay chips
(PDCs) designed primarily for very accurate differential
ECL input edge placement applications.
The delay section consists of a chain of gates and a
linear ramp delay adjustment organized as shown in the
logic diagram. The first two delay elements feature gates
that have been modified to have delays 1.25 and 1.5
times the basic gate delay of approximately 80ps. These
two elements provide the E196 with a digitally-selectable
resolution of approximately 20ps. The required device
delay is selected by the seven address inputs D[0:6],
which are latched on-chip by a high signal on the latch
enable (LEN) control. If the LEN signal is either LOW or
left floating, then the latch is transparent.
The FTUNE input takes an analog coltage and applies
it to an internal linear ramp for reducing the 20s resolution
still further. The FTUNE input is what differentiates the
E196 from the E195.
An eighth latched input, D7, is provided for cascading
multiple PDCs for increased programmable range. The
cascade logic allows full control of multiple PDCs, at the
expense of only a single added line to the data bus for
each additional PDC, without the need for any external
gating.
20ps digital step resolution
Linear input for tighter resolution
>1GHz bandwidth
On-chip cascade circuitry
s
75Kk
input pulldown resistor
s
Fully compatible with Motorola MC10E/100E196
s
Available in 28-pin PLCC package
PIN NAMES
Pin
IN/IN
EN
D[0:7]
Q/Q
LEN
SET MIN
SET MAX
CASCADE
FTUNE
V
CCO
Function
Signal Input
Input Enable
Mux Select Inputs
Signal Output
Latch Enable
Minimum Delay Set
Maximum Delay Set
Cascade Signal
Linear Voltage Input
V
CC
to Output
M9999-032006
hbwhelp@micrel.com or (408) 955-1690
Rev.: H
Amendment: /0
1
Issue Date: March 2006

SY100E196JYTR Related Products

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Description PROGRAMMABLE DELAY CHIP WITH ANALOG INPUT PROGRAMMABLE DELAY CHIP WITH ANALOG INPUT PROGRAMMABLE DELAY CHIP WITH ANALOG INPUT PROGRAMMABLE DELAY CHIP WITH ANALOG INPUT PROGRAMMABLE DELAY CHIP WITH ANALOG INPUT PROGRAMMABLE DELAY CHIP WITH ANALOG INPUT PROGRAMMABLE DELAY CHIP WITH ANALOG INPUT PROGRAMMABLE DELAY CHIP WITH ANALOG INPUT PROGRAMMABLE DELAY CHIP WITH ANALOG INPUT PROGRAMMABLE DELAY CHIP WITH ANALOG INPUT
package instruction QCCJ, - - - - LEAD FREE, PLASTIC, LCC-28 QCCJ, LCC-28 QCCJ, QCCJ,
Reach Compliance Code compli - - - - compli compli compliant compli compli
series 100E - - - - 10E 10E 10E 100E 100E
JESD-30 code S-PQCC-J28 - - - - S-PQCC-J28 S-PQCC-J28 S-PQCC-J28 S-PQCC-J28 S-PQCC-J28
length 11.48 mm - - - - 11.48 mm 11.48 mm 11.48 mm 11.48 mm 11.48 mm
Logic integrated circuit type SILICON DELAY LINE - - - - SILICON DELAY LINE SILICON DELAY LINE SILICON DELAY LINE SILICON DELAY LINE SILICON DELAY LINE
Number of functions 1 - - - - 1 1 1 1 1
Number of taps/steps 127 - - - - 127 127 127 127 127
Number of terminals 28 - - - - 28 28 28 28 28
Output polarity COMPLEMENTARY - - - - COMPLEMENTARY COMPLEMENTARY COMPLEMENTARY COMPLEMENTARY COMPLEMENTARY
Package body material PLASTIC/EPOXY - - - - PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code QCCJ - - - - QCCJ QCCJ QCCJ QCCJ QCCJ
Package shape SQUARE - - - - SQUARE SQUARE SQUARE SQUARE SQUARE
Package form CHIP CARRIER - - - - CHIP CARRIER CHIP CARRIER CHIP CARRIER CHIP CARRIER CHIP CARRIER
programmable delay line YES - - - - YES YES YES YES YES
Maximum seat height 4.57 mm - - - - 4.57 mm 4.57 mm 4.57 mm 4.57 mm 4.57 mm
surface mount YES - - - - YES YES YES YES YES
technology ECL - - - - ECL ECL ECL ECL ECL
Terminal form J BEND - - - - J BEND J BEND J BEND J BEND J BEND
Terminal pitch 1.27 mm - - - - 1.27 mm 1.27 mm 1.27 mm 1.27 mm 1.27 mm
Terminal location QUAD - - - - QUAD QUAD QUAD QUAD QUAD
Total delay nominal (td) 3.63 ns - - - - 3.63 ns 3.63 ns 3.63 ns 3.63 ns 3.63 ns
width 11.48 mm - - - - 11.48 mm 11.48 mm 11.48 mm 11.48 mm 11.48 mm
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