BCM8727
®
Brief
SUMMARY OF BENEFITS
•
Single-reference clock input enables use of low-cost 156.25
MHz oscillator.
DUAL-CHANNEL 10-G
B
E SFI-
TO
-XAUI™ TRANSCEIVER
WITH
EDC
FEATURES
•
Dual-channel SFI-to-XAUI™ transceiver
•
Integrated microcontroller and AGC with a wide dynamic
range
•
Supports low-cost SFP+ copper twin-ax up to 15m
•
LRM mode supports 300m of Multimode Fiber (MMF),
exceeding the IEEE 802.3aq standard.
•
Supports SFP+ SR, LR, and LRM optical interfaces and up to
15m of direct attached copper
•
Programmable amplitude control on 10G serial transmitter
interface
•
PMD transmit preemphasis for flexible placement of Physical
Layer (PHY)
•
Standard two-wire Broadcom Serial Interface (BSC) support
for external E2, XFP, SFP, SFP+
•
Support for module present detection and configuring of
BCM8727 accordingly
•
MDIO interface compliant to IEEE802.3ae Clause 45 with
extended indirect address register access
•
Multirate 10 GbE and 1 GbE support for legacy interfaces
•
Support for XFP/XFI interfaces
•
Physical Medium Dependent (PMD) interface: serial 10.3125
Gbps CML
APPLICATIONS
•
High-density Ethernet Switching and Routing Platforms
•
Next-generation Blade Servers
•
SFP+ optical SR, LR, and LRM modules
•
SFP+ copper twin-ax
•
PCS 64B/66B scrambler/descrambler
•
XGXS 8B/10B error detection ENDEC
•
XAUI link synchronization/deskew
•
4-lane XAUI interface (3.125 Gbps)
•
Built-In Self-Test (BIST) on 10G serial and XAUI interfaces
•
Power dissipation: 2.4W
•
Core supply—1.0V, I/O—3.3V
•
Small 19 mm x 19 mm BGA package, 1-mm ball pitch
BCM8727 Functional Block Diagram
BCM8727
XAUI Interface 1
PCS/PMA
XGXS
XGXS
LRM-
EDC
SFI 1
SFP+
10.3125
Gbps
MAC/
Switch
RS
XAUI Interface 2
MDC MDIO
Management
Interface
LRM-
EDC
SFI 2
SFP+
10.3125
Gbps
OVERVIEW
XAOP
Gearbox
XAON
Elastic FIFO
Randomizer
3.125 Gbps
Serializer
8B/10B
Encoder
XDOP
XDON
Serializer
8B/10B
Encoder
64/66B
Synchronizer
Descrambler
Decoder
CDR and
Deserializer
MMF EDC
DSP Core
PDIP
AGC
PDIN
322.26M
312.5M
156.25 MHz
REFCLKP
REFCLKN
REFCK
RefClk
Block
32K
ROM
Sync. Detect
Lane Sync
8B/10B
Decoder
312.5M
uC
SPI
SPI
312.5M
XAIP
XAIN
Elastic FIFO
DLL and
Deserializer
3.125 Gbps
Lane
Alignment
FIFO
16K
RAM
322.26M
XDIP
XDIN
DLL and
Deserializer
Sync. Detect
Lane Sync
8B/10B
Decoder
64/66B
Encoder
Scrambler
Gearbox
CMU and
Serializer
Lane
Alignment
FIFO
XAOP
Gearbox
XAON
Elastic FIFO
Randomizer
3.125 Gbps
Serializer
8B/10B
Encoder
XDOP
XDON
Serializer
8B/10B
Encoder
64/66B
Synchronizer
Descrambler
Decoder
CDR and
Deserializer
MMF EDC
DSP Core
AGC
PDIN
322.26M
312.5M
REFCK
RefClk
Block
32K
ROM
Sync. Detect
Lane Sync
8B/10B
Decoder
312.5M
uC
SPI
SPI
312.5M
XAIP
XAIN
Elastic FIFO
DLL and
Deserializer
3.125 Gbps
Lane
Alignment
FIFO
16K
RAM
322.26M
XDIP
XDIN
DLL and
Deserializer
Sync. Detect
Lane Sync
8B/10B
Decoder
64/66B
Encoder
Scrambler
Gearbox
CMU and
Serializer
Lane
Alignment
FIFO
MDIO
MDC
PRTAD[4:1]
RSTB
LASI
SDA
SCL
Management
and
Control
Interface
BSC Serial
Interface
JTAG
Optics
Control
and
Status
OPRXLOS
MOD_ABS
OPTXENB
OPRSTB
BCM8727 Block Diagram
The BCM8727 is a dual-channel 10-GbE SFI-to-XAUI transceiver that
incorporates an Electronic Dispersion Compensation (EDC) equalizer
supporting SFP+ line-card applications.
The BCM8727 is a multirate PHY targeted for SMF, MMF, or copper
twin-ax applications interfacing to both limiting-based and linear-based
SFP+ and SFP modules. The BCM8727 is fully compliant to the 10-GbE
IEEE 802.3aq standard and also supports 1000BASE-X for 1-GbE
operation.
The BCM8727 is developed using an all-DSP high-speed front-end
providing the highest performance and most flexibility for line-card
designers. An on-chip microcontroller implements the control algorithm
for the DSP core.
On-chip clock synthesis is performed by the high-frequency, low-jitter,
Phase-Locked Loops (PLLs) for the PMD and XAUI output retimers.
Individual PMD and XAUI clock recovery is performed on the device by
synchronizing directly to the respective incoming data streams. An
external 156.25 MHz reference clock input is required for each port.
The BCM8727 Ethernet LRM PHY device is a fully integrated SerDes
(10.3125 Gbps) interface device performing the extension functions for
a 10-Gigabit serial Ethernet Reconciliation Sublayer (RS) interface. The
XGXS, PCS, and PMA functions include 8B/10B coding, 64B/66B
coding, SerDes, Clock Multiplication Unit (CMU), and Clock and Data
Recovery (CDR).
The BCM8727 is available in a 19 mm x 19 mm, 1 mm pitch, 324-pin
BGA, RoHS-compliant package. The BCM8727 supports a footprint-
compatible layout with the BCM8726 dual LRM PHY.
Broadcom
®
, the pulse logo,
Connecting everything
®
, and the Connecting everything logo are among
the trademarks of Broadcom Corporation and/or its affiliates in the United States, certain other countries
and/or the EU. Any other trademarks or trade names mentioned are the property of their respective
owners.
®
BROADCOM CORPORATION
5300 California Avenue
Irvine, California 92617
© 2009 by BROADCOM CORPORATION. All rights reserved.
8727-PB00-R
03/16/09
10.3125 Gbps
PDOP
PDON
CMU
156.25M
10.3125 Gbps
PDOP
PDON
PDIP
CMU
156.25M
Phone: 949-926-5000
Fax: 949-926-5203
E-mail: info@broadcom.com
Web: www.broadcom.com