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SY100E154JC

Description
5-BIT 2:1 MUX-LATCH
Categorylogic    logic   
File Size60KB,4 Pages
ManufacturerMicrochip
Websitehttps://www.microchip.com
Download Datasheet Parametric View All

SY100E154JC Overview

5-BIT 2:1 MUX-LATCH

SY100E154JC Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerMicrochip
package instructionPLASTIC, LCC-28
Reach Compliance Code_compli
Other featuresFIVE 2:1 MUX FOLLOWED BY LATCH
series100E
JESD-30 codeS-PQCC-J28
JESD-609 codee0
length11.48 mm
Logic integrated circuit typeD LATCH
Humidity sensitivity level1
Number of digits5
Number of functions1
Number of entries2
Number of terminals28
Maximum operating temperature85 °C
Minimum operating temperature
Output characteristicsOPEN-EMITTER
Output polarityCOMPLEMENTARY
Package body materialPLASTIC/EPOXY
encapsulated codeQCCJ
Encapsulate equivalent codeLDCC28,.5SQ
Package shapeSQUARE
Package formCHIP CARRIER
Peak Reflow Temperature (Celsius)240
power supply-4.5 V
Maximum supply current (ICC)105 mA
Prop。Delay @ Nom-Su0.7 ns
propagation delay (tpd)0.75 ns
Certification statusNot Qualified
Maximum seat height4.57 mm
surface mountYES
technologyECL
Temperature levelCOMMERCIAL EXTENDED
Terminal surfaceTin/Lead (Sn85Pb15)
Terminal formJ BEND
Terminal pitch1.27 mm
Terminal locationQUAD
Maximum time at peak reflow temperature30
Trigger typeLOW LEVEL
width11.48 mm
Base Number Matches1
Micrel, Inc.
5-BIT 2:1
MUX-LATCH
SY10E154
SY100E154
SY10E154
SY100E154
FEATURES
s
s
s
s
s
750ps max. LEN to output
Extended 100E V
EE
range of –4.2V to –5.5V
700ps max. D to output
Differential outputs
Asynchronous Master Reset
DESCRIPTION
The SY10/100E154 offer five 2:1 multiplexers followed
by latches with differential outputs, designed for use in
new, high-performance ECL systems. The two external
Latch-Enable signals (LEN
1
, LEN
2
) are gated through a
logical OR operation before use as control for the five
latches. When both LEN
1
and LEN
2
are at a logic LOW, the
latches are transparent, thus presenting the data from the
multiplexers at the output pins. If either LEN
1
or LEN
2
(or
both) are at a logic HIGH, the outputs are latched.
The multiplexer operation is controlled by the SEL(Select)
signal which selects one of the two bits of input data at each
mux to be passed through.
The MR (Master Reset) signal operates asynchronously
to make all Q outputs go to a logic LOW.
s
Dual latch-enables
s
Fully compatible with industry standard 10KH,
100K ECL levels
s
Internal 75K
input pulldown resistors
s
Fully compatible with Motorola MC10E/100E154
s
Available in 28-pin PLCC package
BLOCK DIAGRAM
PIN NAMES
Pin
Function
Input Data a
Input Data b
Data Select Input
Latch Enables
Master Reset
True Outputs
Inverted Outputs
V
CC
to Output
D
0a
MUX
D
0b
D
1a
MUX
D
1b
D
2a
MUX
D
2b
D
3a
MUX
D
3b
D
4a
MUX
D
4b
SEL
LEN
1
LEN
2
MR
SEL
SEL
SEL
SEL
SEL
D
Q
Q
0
Q
0
D
0a
–D
4a
D
0b
–D
4b
SEL
E Q
NR
D
Q
Q
1
Q
1
LEN
1
, LEN
2
MR
Q
0
–Q
4
Q
0
–Q
4
E Q
NR
D
Q
Q
2
Q
2
V
CCO
E Q
NR
D
Q
Q
3
Q
3
E Q
NR
D
Q
Q
4
Q
4
E Q
N R
M9999-032006
hbwhelp@micrel.com or (408) 955-1690
Rev.: E
Amendment: /0
1
Issue Date: March 2006

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