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SY100E131JI

Description
100E SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PQCC28
Categorylogic    logic   
File Size92KB,5 Pages
ManufacturerMicrochip
Websitehttps://www.microchip.com
Download Datasheet Parametric View All

SY100E131JI Overview

100E SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PQCC28

SY100E131JI Parametric

Parameter NameAttribute value
MakerMicrochip
package instructionPLCC-28
Reach Compliance Codecompli
Other featuresLVECL MODE: VCC = 0V WITH VEE = -4.2V TO -5.5V
series100E
JESD-30 codeS-PQCC-J28
length11.48 mm
Logic integrated circuit typeD FLIP-FLOP
Number of digits4
Number of functions1
Number of terminals28
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Output characteristicsOPEN-EMITTER
Output polarityCOMPLEMENTARY
Package body materialPLASTIC/EPOXY
encapsulated codeQCCJ
Encapsulate equivalent codeLDCC28,.5SQ
Package shapeSQUARE
Package formCHIP CARRIER
Maximum supply current (ICC)81 mA
propagation delay (tpd)0.675 ns
Maximum seat height4.57 mm
surface mountYES
technologyECL
Temperature levelINDUSTRIAL
Terminal formJ BEND
Terminal pitch1.27 mm
Terminal locationQUAD
Trigger typePOSITIVE EDGE
width11.48 mm
minfmax1100 MHz
NOT RECOMMENDED FOR NEW DESIGNS
Micrel, Inc.
4-BIT D
FLIP-FLOP
SY10E131
SY100E131
SY10E131
SY100E131
FEATURES
s
s
s
s
s
s
1100MHz min. toggle frequency
Extended 100E V
EE
range of –4.2V to –5.5V
Differential output
Individual and common clocks
Indivldual asynchronous reset
Paired asynchronous sets
DESCRIPTION
The SY10/100E131 are high-speed quad master slave
D-type flip-flops with differential outputs designed for use
in new, high-performance ECL systems. The flip-flops may
be individually clocked by holding C
C
(Common Clock) at
a logic LOW and then using the four individual CE (Clock
Enable CE
0
–CE
3
) inputs to accomplish such clocking.
Alternatively, all four flip-flops can be clocked in common
by holding the CE inputs LOW and then using C
C
to clock
the data. In the common clock mode, the CE input acts as
a control that passes the C
C
signal to the flip-flop. Data is
clocked into the flip-flop on the rising edge of the output of
the logical OR operation between CE and C
C
(data enters
the master when both C
C
and CE are LOW and data
transfers to the slave when either CE or C
C,
or both, go
HIGH).
Asynchronous set and reset controls are provided. The
reset controls are individual and the set controls are
pairwise.
s
Fully compatible with Industry standard 10KH,
100K ECL levels
s
Internal 75K
input pulldown resistors
s
Fully compatible with Motorola MC10E/100E131
s
Available in 28-pin PLCC package
PIN NAMES
Pin
D
0
-D
3
CE
0
-CE
3
R
0
-R
3
C
C
S
03
, S
12
Q
0
-Q
3
Q
0
-Q
3
V
CCO
Function
Data Inputs
Clock Enables (Individual)
Resets
Common Clock
Sets (paired)
True Outputs
Inverting Outputs
V
CC
to Output
M9999-032006
hbwhelp@micrel.com or (408) 955-1690
Rev.: H
Amendment: /0
1
Issue Date: March 2006
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