SY100E111LJI datasheet, PDF - EEWORLD Datasheet

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SY100E111LJI: Description5V/3.3V 1:9 DIFFERENTIAL CLOCK DRIVER (w/o ENABLE); Categorylogic logic; File Size74KB，6 Pages; ManufacturerMicrochip; Websitehttps://www.microchip.com

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SY100E111LJI Overview

5V/3.3V 1:9 DIFFERENTIAL CLOCK DRIVER (w/o ENABLE)

SY100E111LJI Parametric

Parameter Name	Attribute value
Maker	Microchip
package instruction	QCCJ,
Reach Compliance Code	compli
series	100E
Input adjustment	DIFFERENTIAL
JESD-30 code	S-PQCC-J28
length	11.48 mm
Logic integrated circuit type	LOW SKEW CLOCK DRIVER
Number of functions	1
Number of inverted outputs
Number of terminals	28
Actual output times	18
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	QCCJ
Package shape	SQUARE
Package form	CHIP CARRIER
propagation delay (tpd)	0.78 ns
Same Edge Skew-Max（tskwd）	0.075 ns
Maximum seat height	4.57 mm
surface mount	YES
technology	ECL
Temperature level	INDUSTRIAL
Terminal form	J BEND
Terminal pitch	1.27 mm
Terminal location	QUAD
width	11.48 mm

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Micrel, Inc.

5V/3.3V 1:9 DIFFERENTIAL

CLOCK DRIVER (w/o ENABLE)

Precison Edge

SY10E111A/L

Precision Edge

SY100E111A/L

SY10E111A/L

SY100E111A/L

FEATURES

5V and 3.3V power supply options

200ps part-to-part skew

50ps output-to-output skew

Differential design

output

Voltage and temperature compensated outputs

Precision Edge

DESCRIPTION

The SY10/100E111A/L are low skew 1-to-9 differential

driver designed for clock distribution in mind. The

SY10/100E111A/L's function and performance are similar to

the popular SY10/100E111, with the improvement of lower

jitter and the added feature of low voltage operation. It accepts

one signal input, which can be either differential or single-

ended if the V

output is used. The signal is fanned out to 9

identical differential outputs.

The E111A/L are specifically designed, modeled and

produced with low skew as the key goal. Optimal design and

layout serve to minimize gate to gate skew within a device, and

empirical modeling is used to determine process control limits

that ensure consistent t

distributions from lot to lot. The net

result is a dependable, guaranteed low skew device.

To ensure that the tight skew specification is met it is

necessary that both sides of the differential output are

terminated into 50Ω, even if only one side is being used. In

most applications, all nine differential pairs will be used and

therefore terminated. In the case where fewer that nine pairs

are used, it is necessary to terminate at least the output pairs

on the same package side as the pair(s) being used on that

side, in order to maintain minimum skew. Failure to do this will

result in small degradations of propagation delay (on the order

of 10-20ps) of the output(s) being used which, while not being

catastrophic to most designs, will mean a loss of skew margin.

The E111A/L, as with most other ECL devices, can be

operated from a positive V

supply in PECL mode. This

allows the E111A/L to be used for high performance clock

distribution in +5V/+3.3V systems. Designers can take

advantage of the E111A/L's performance to distribute low

skew clocks across the backplane or the board. In a PECL

environment, series or Thevenin line terminations are typically

used as they require no additional power supplies. For

systems incorporating GTL, parallel termination offers the

lowest power by taking advantage of the 1.2V supply as

terminating voltage.

75K

Ω

input pulldown resistors

Fully compatible with Motorola MC100LVE111

Available in 28-pin PLCC package

BLOCK DIAGRAM

PIN NAMES

IN, IN

, Q

— Q

, Q

CCO

Function

Differential Input Pair

Differential Outputs

Output

to Output

Precision Edge is a registered trademark of Micrel, Inc.

M9999-032006

hbwhelp@micrel.com or (408) 955-1690

Rev.: J

Amendment: /0

March 2006

Rev. Date:

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