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SY100E111JCTR

Description
1:9 DIFFERENTIAL CLOCK DRIVER WITH ENABLE
Categorylogic    logic   
File Size93KB,4 Pages
ManufacturerMicrochip
Websitehttps://www.microchip.com
Download Datasheet Parametric View All

SY100E111JCTR Overview

1:9 DIFFERENTIAL CLOCK DRIVER WITH ENABLE

SY100E111JCTR Parametric

Parameter NameAttribute value
MakerMicrochip
package instructionLCC-28
Reach Compliance Codecompli
series100E
Input adjustmentDIFFERENTIAL
JESD-30 codeS-PQCC-J28
length11.48 mm
Logic integrated circuit typeLOW SKEW CLOCK DRIVER
Number of functions1
Number of inverted outputs
Number of terminals28
Actual output times18
Package body materialPLASTIC/EPOXY
encapsulated codeQCCJ
Package shapeSQUARE
Package formCHIP CARRIER
propagation delay (tpd)0.73 ns
Same Edge Skew-Max(tskwd)0.05 ns
Maximum seat height4.57 mm
surface mountYES
technologyECL
Terminal formJ BEND
Terminal pitch1.27 mm
Terminal locationQUAD
width11.48 mm
NOT RECOMMENDED FOR NEW DESIGNS
Micrel, Inc.
1:9 DIFFERENTIAL CLOCK
DRIVER WITH ENABLE
SY10E111
SY100E111
SY10E111
SY100E111
FEATURES
s
s
s
s
Low skew
Extended 100E V
EE
range of –4.2V to –5.5V
Guaranteed skew limits
Differential design
DESCRIPTION
The SY10/100E111 are low skew 1-to-9 differential
drivers designed for clock distribution in new, high-
performance ECL systems. They accept one differential or
single-ended input, with V
BB
used for single-ended
operation. The signal is fanned out to nine identical
differential outputs. An enable input is also provided such
that a logic HIGH disables the device by forcing all Q
outputs LOW and all /Q outputs HIGH.
The device is specifically designed and produced for low
skew. The interconnect scheme and metal layout are
carefully optimized for minimal gate-to-gate skew within
the device. Wafer characterization and process control
ensure consistent distribution of propagation delay from lot
to lot. Since the E111 shares a common set of “basic”
processing with the other members of the ECLinPS™
family, wafer characterization at the point of device
personalization allows for tighter control of parameters,
including propagation delay.
To ensure that the skew specification is met, it is
necessary that both sides of the differential output are
terminated into 50Ω, even if only one side is being used. ln
most applications, all nine differential pairs will be used
and, therefore, terminated. In the case where fewer than
nine pairs are used, it is necessary to terminate at least the
output pairs on the same package side (i.e. sharing the
same V
CCO
as the pair(s) being used on that side) in order
to maintain minimum skew.
The V
BB
output is intended for use as a reference
voltage for single-ended reception of ECL signals to that
device only. When using V
BB
for this purpose, it is
recommended that V
BB
is decoupled to V
CC
via a 0.01µF
capacitor.
s
V
BB
output
s
Enable input
s
Fully compatible with industry standard 10KH, 100K
I/O levels
s
75K
input pulldown resistors
s
Fully compatible with ON Semiconductor
MC10E/100E111
s
Available in 28-pin PLCC package
BLOCK DIAGRAM
Q
0
Q
0
Q
1
Q
1
Q
2
Q
2
Q
3
Q
3
IN
IN
EN
Q
5
Q
6
Q
4
Q
4
Q
5
PIN NAMES
Pin
Function
Differential Input Pair
Enable Input
Differential Outputs
V
BB
Output
V
CC
to Output
Q
6
Q
7
Q
7
Q
8
V
BB
Q
8
IN, /IN
/EN
Q0, /Q0 — Q8, /Q8
V
BB
V
CCO
M9999-032006
hbwhelp@micrel.com or (408) 955-1690
Rev.: E
Amendment: /0
1
Issue Date: March 2006
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