STR911FAM34X6T datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > The embedded processor and controller> Microcontrollers and processors> STR911FAM34X6T

STR911FAM34X6T: Description32-BIT, FLASH, 96 MHz, RISC MICROCONTROLLER, PBGA144; CategoryThe embedded processor and controller Microcontrollers and processors; File Size766KB，108 Pages; ManufacturerSTMicroelectronics; Websitehttp://www.st.com/

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STR911FAM34X6T Overview

32-BIT, FLASH, 96 MHz, RISC MICROCONTROLLER, PBGA144

STR911FAM34X6T Parametric

Parameter Name	Attribute value
Maker	STMicroelectronics
Parts packaging code	QFP
package instruction	LFQFP,
Contacts	80
Reach Compliance Code	unknow
Has ADC	YES
Address bus width
bit size	32
maximum clock frequency	25 MHz
DAC channel	NO
DMA channel	YES
External data bus width
JESD-30 code	S-XQFP-G80
length	12 mm
Number of I/O lines	40
Number of terminals	80
On-chip program ROM width	8
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
PWM channel	YES
Package body material	UNSPECIFIED
encapsulated code	LFQFP
Package shape	SQUARE
Package form	FLATPACK, LOW PROFILE, FINE PITCH
Certification status	Not Qualified
RAM (bytes)	65536
rom(word)	524288
ROM programmability	FLASH
Maximum seat height	1.6 mm
speed	96 MHz
Maximum supply voltage	2 V
Minimum supply voltage	1.65 V
Nominal supply voltage	1.8 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	QUAD
width	12 mm
uPs/uCs/peripheral integrated circuit type	MICROCONTROLLER, RISC

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STR91xFAxxx

ARM966E-S™ 16/32-bit Flash MCU with Ethernet, USB, CAN,

AC motor control, 4 timers, ADC, RTC, DMA

Datasheet

production data

Features

•

16/32-bit 96 MHz ARM9E based MCU

– ARM966E-S™ RISC core: Harvard archi-

tecture, 5-stage pipeline, Tightly-Coupled

Memories (SRAM and Flash)

– STR91xFA implementation of core adds

high-speed burst Flash memory interface,

instruction prefetch queue, branch cache

– Up to 96 MIPS directly from Flash memory

– Single-cycle DSP instructions supported

– Binary compatible with ARM7 code

•

Dual burst Flash memories, 32-bits wide

– 256 KB/512 KB/1 MB/2 MB main Flash

– 32 KB/128 KB secondary Flash

– Sequential Burst operation up to 96 MHz

– 100 K min erase cycles, 20 yr min retention

•

SRAM, 32-bits wide

– 64K or 96K bytes, optional battery backup

•

9 programmable DMA channels

•

Clock, reset, and supply management

– Internal oscillator operating with external

4-25 MHz crystal

– Internal PLL up to 96 MHz

– Real-time clock provides calendar

functions, tamper, and wake-up functions

– Reset Supervisor monitors supply voltage,

watchdog, wake-up unit, external reset

– Brown-out monitor

– Run, Idle, and Sleep Mode as low as 50 uA

•

Vectored interrupt controller (VIC)

– 32 IRQ vectors, 30 interrupt pins

– Branch cache minimizes interrupt latency

•

8-channel, 10-bit A/D converter (ADC)

– 0 to 3.6 V range, 0.7 usec conversion

•

10 Communication interfaces

– 10/100 Ethernet MAC with DMA and MII

– USB Full-speed (12 Mbps) slave device

– CAN interface (2.0B Active)

LQFP80 12 x12mm

LQFP128 14 x

14mm

LFBGA144 10 x 10 mm

– 3 16550-style UARTs with IrDA protocol

– 2 Fast I

C, 400 kHz

– 2 channels for SPI, SSI™, or

MICROWIRE™

•

External Memory Interface (EMI)

– 8- or 16-bit data, up to 24-bit addressing

– Static Async modes for LQFP128

– Additional burst synchronous modes for

LFBGA144

•

Up to 80 I/O pins (muxed with interfaces)

•

16-bit standard timers (TIM)

– 4 timers each with 2 input capture, 2 output

compare, PWM and pulse count modes

•

3-Phase induction motor controller (IMC)

•

JTAG interface with boundary scan

•

Embedded trace module (ARM

ETM9™)

Table 1. Device summary

Reference

STR91xFAx32

STR91xFAx42

STR91xFAx44

STR91xFAx46

STR91xFAx47

Part number

STR910FAM32, STR910FAW32,

STR910FAZ32, STR912FAW32

STR911FAM42, STR911FAW42,

STR912FAW42, STR912FAZ42

STR911FAM44 STR911FAW44

STR912FAW44, STR912FAZ44

STR911FAM46, STR911FAW46,

STR912FAW46, STR912FAZ46

STR911FAM47, STR911FAW47,

STR912FAW47, STR912FAZ47

March 2015

This is information on a product in full production.

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www.st.com

Contents

STR91xFAxxx

Contents

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3.1

3.2

3.3

3.4

System-in-a-package (SiP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Package choice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

ARM966E-S CPU core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Burst Flash memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3.4.1

3.4.2

3.4.3

Pre-fetch queue (PFQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Branch cache (BC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Management of literals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Battery backup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.5

SRAM (64 Kbytes or 96 Kbytes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.5.1

3.5.2

3.6

3.7

DMA data movement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Non-volatile memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.7.1

3.7.2

Primary Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Secondary Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Product ID and revision level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

FIQ handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

IRQ handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Master clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Reference clock (RCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

AHB clock (HCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

APB clock (PCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Flash memory interface clock (FMICLK) . . . . . . . . . . . . . . . . . . . . . . . . 22

UART and SSP clock (BRCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

External memory interface bus clock (BCLK) . . . . . . . . . . . . . . . . . . . . 22

3.8

3.9

One-time-programmable (OTP) memory . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.8.1

3.9.1

3.9.2

3.9.3

Vectored interrupt controller (VIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.10

Clock control unit (CCU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.10.1

3.10.2

3.10.3

3.10.4

3.10.5

3.10.6

3.10.7

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3.10.8

3.10.9

Contents

USB interface clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Ethernet MAC clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.10.10 External RTC calibration clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.10.11 Operation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.11

Flexible power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.11.1

3.11.2

3.11.3

Run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Independent A/D converter supply and reference voltage . . . . . . . . . . . 24

Battery supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Supply voltage brownout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Supply voltage dropout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

External RESET_INn pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

JTAG debug command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Tamper detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

3.12

Voltage supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3.12.1

3.12.2

3.13

System supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

3.13.1

3.13.2

3.13.3

3.13.4

3.13.5

3.13.6

3.13.7

3.14

3.15

Real-time clock (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

JTAG interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

3.15.1

3.15.2

3.15.3

3.15.4

In-system-programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Boundary scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

CPU debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

JTAG security bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

3.16

3.17

3.18

Embedded trace module (ARM ETM9, v. r2p2) . . . . . . . . . . . . . . . . . . . . 30

Ethernet MAC interface with DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

USB 2.0 slave device interface with DMA . . . . . . . . . . . . . . . . . . . . . . . . 31

3.18.1

3.18.2

3.18.3

Packet buffer interface (PBI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Suspend mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

3.19

3.20

3.21

3.22

CAN 2.0B interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

UART interfaces with DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

3.20.1

DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

I2C interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

SSP interfaces (SPI, SSI, and MICROWIRE) with DMA . . . . . . . . . . . . . 34

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3.22.1

STR91xFAxxx

DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

3.23

3.24

3.25

3.26

3.27

General purpose I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

A/D converter (ADC) with DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

3.24.1

3.25.1

DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Standard timers (TIM) with DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Three-phase induction motor controller (IMC) . . . . . . . . . . . . . . . . . . . . . 37

External memory interface (EMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Related documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

5.1

5.2

LFBGA144 ball connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Default pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

5.2.1

General notes on pin usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

6.1

6.2

6.3

6.4

Buffered and non-buffered writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

System (AHB) and peripheral (APB) buses . . . . . . . . . . . . . . . . . . . . . . . 54

SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Two independent Flash memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

6.4.1

6.4.2

Default configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Optional configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

6.5

STR91xFA memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

7.1

Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

7.1.1

7.1.2

7.1.3

7.1.4

7.1.5

Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

7.2

7.3

7.4

4/108

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

7.3.1

Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 61

RESET_INn and power-on-reset characteristics . . . . . . . . . . . . . . . . . . . 62

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7.5

7.6

7.7

LVD electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

7.5.1

7.6.1

7.7.1

7.7.2

7.7.3

7.7.4

LVD delay timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Typical power consumption for frequencies below 10 MHz . . . . . . . . . . 65

Main oscillator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 67

X1_CPU external clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

RTC clock generated from a crystal/ceramic resonator . . . . . . . . . . . . . 68

PLL electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

SRAM characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Functional EMS (electro magnetic susceptibility) . . . . . . . . . . . . . . . . . 72

Electro magnetic interference (EMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 73

Electro-static discharge (ESD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Static latch-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Designing hardened software to avoid noise problems . . . . . . . . . . . . . 74

Electrical sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

7.8

Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

7.8.1

7.8.2

7.9

EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

7.9.1

7.9.2

7.9.3

7.9.4

7.9.5

7.9.6

7.9.7

7.10

7.11

I/O characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

External memory bus timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

7.11.1

7.11.2

Asynchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Synchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

10/100 Ethernet MAC electrical characteristics . . . . . . . . . . . . . . . . . . . 84

USB electrical interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 86

CAN interface electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 86

I2C electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

SPI electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

7.12

Communication interface electrical characteristics . . . . . . . . . . . . . . . . . 84

7.12.1

7.12.2

7.12.3

7.12.4

7.12.5

7.13

ADC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Device marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

8.1

8.2

STR91xFAx32 / STR91xFAx42 / STR91xFAx44 . . . . . . . . . . . . . . . . . . . 93

STR91xFAx46 / STR91xFAx47 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

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