BLC9G20XS-400AVT
Power LDMOS transistor
Rev. 3 — 24 November 2017
Product data sheet
1. Product profile
1.1 General description
400 W LDMOS packaged asymmetric Doherty power transistor for base station
applications at frequencies from 1805 MHz to 1880 MHz and 1930 MHz to 1995 MHz.
Table 1.
Typical performance
Typical RF performance at T
case
= 25
C in an asymmetrical Doherty production test circuit.
V
DS
= 32 V; I
Dq
= 800 mA (main); V
GS(amp)peak
= 0.5 V, unless otherwise specified.
Test signal
1-carrier W-CDMA
[1]
f
(MHz)
1805 to 1880
V
DS
(V)
32
P
L(AV)
(W)
87
G
p
(dB)
16.2
D
(%)
45
ACPR
(dBc)
39
[1]
Test signal: 1-carrier W-CDMA; 3GPP test model 1; 64 DPCH; PAR = 9.6 dB at 0.01 % probability on
CCDF.
1.2 Features and benefits
Excellent ruggedness
High efficiency
Low thermal resistance providing excellent thermal stability
Lower output capacitance for improved performance in Doherty applications
Designed for low memory effects providing excellent digital pre-distortion capability
Internally matched for ease of use
Integrated ESD protection
Compliant to Directive 2002/95/EC, regarding Restriction of Hazardous Substances
(RoHS)
1.3 Applications
RF power amplifiers for base stations and multi carrier applications in the 1805 MHz to
1880 MHz and 1930 MHz to 1995 MHz frequency range
BLC9G20XS-400AVT
Power LDMOS transistor
2. Pinning information
Table 2.
Pin
1
2
3
4
5
6
7
[1]
Pinning
Description
drain2 (peak)
drain1 (main)
gate1 (main)
gate2 (peak)
source
video decoupling (peak)
video decoupling (main)
1, 6
aaa-014884
Simplified outline
7
2
1
6
5
Graphic symbol
2, 7
3
3
[1]
4
5
4
Connected to flange.
3. Ordering information
Table 3.
Ordering information
Package
Name
BLC9G20XS-400AVT
-
Description
air cavity plastic earless flanged package;
6 leads
Version
SOT1258-4
Type number
4. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
V
DS
V
GS(amp)main
V
GS(amp)peak
T
stg
T
j
T
case
[1]
Parameter
drain-source voltage
main amplifier gate-source voltage
peak amplifier gate-source voltage
storage temperature
junction temperature
case temperature
Conditions
Min
-
6
6
65
[1]
Max
65
+13
+13
+150
225
+125
Unit
V
V
V
C
C
C
-
40
operating
[1]
Continuous use at maximum temperature will affect the reliability, for details refer to the online MTF
calculator.
5. Thermal characteristics
Table 5.
R
th(j-c)
Thermal characteristics
Conditions
Typ
Unit
thermal resistance from junction V
DS
= 32 V; I
Dq
= 800 mA (main);
to case
V
GS(amp)peak
= 0,4 V; T
case
= 80
C
P
L
= 85 W
P
L
= 110 W
BLC9G20XS-400AVT
All information provided in this document is subject to legal disclaimers.
Symbol Parameter
0.25
0.26
k/W
k/W
© Ampleon Netherlands B.V. 2017. All rights reserved.
Product data sheet
Rev. 3 — 24 November 2017
2 of 17
BLC9G20XS-400AVT
Power LDMOS transistor
6. Characteristics
Table 6.
DC characteristics
T
j
= 25
C unless otherwise specified.
Symbol Parameter
Main device
V
(BR)DSS
drain-source breakdown voltage V
GS
= 0 V; I
D
= 1.62 mA
V
GS(th)
V
GSq
I
DSS
I
DSX
I
GSS
g
fs
R
DS(on)
gate-source threshold voltage
gate-source quiescent voltage
drain leakage current
drain cut-off current
gate leakage current
forward transconductance
V
DS
= 10 V; I
D
= 162 mA
V
DS
= 32 V; I
D
= 850 mA
V
GS
= 0 V; V
DS
= 32 V
V
GS
= V
GS(th)
+ 3.75 V
V
GS
= 11 V; V
DS
= 0 V
V
DS
= 10 V; I
D
= 8.1 A
65
1.5
-
-
-
-
-
-
2.0
-
32
-
11.5
85
-
2.5
2.8
-
-
V
V
A
A
S
Conditions
Min Typ
Max Unit
1.65 2.15
2.65 V
280 nA
149 m
drain-source on-state resistance V
GS
= V
GS(th)
+ 3.75 V;
I
D
= 5.67 A
Peak device
V
(BR)DSS
drain-source breakdown voltage V
GS
= 0 V; I
D
= 3.0 mA
V
GS(th)
V
GSq
I
DSS
I
DSX
I
GSS
g
fs
R
DS(on)
gate-source threshold voltage
gate-source quiescent voltage
drain leakage current
drain cut-off current
gate leakage current
forward transconductance
V
DS
= 10 V; I
D
= 300 mA
V
DS
= 32 V; I
D
= 1500 mA
V
GS
= 0 V; V
DS
= 32 V
V
GS
= V
GS(th)
+ 3.75 V
V
GS
= 11 V; V
DS
= 0 V
V
DS
= 10 V; I
D
= 15 A
65
1.5
-
-
-
-
-
-
2.0
-
52
-
20.5
46
-
2.5
2.8
-
-
85
V
V
A
A
S
m
1.65 2.15
2.65 V
280 nA
drain-source on-state resistance V
GS
= V
GS(th)
+ 3.75 V;
I
D
= 10.5 A
Table 7.
RF characteristics
Test signal: 1-carrier W-CDMA; PAR = 9.6 dB at 0.01 % probability on the CCDF;
3GPP test model 1; 1 to 64 DPCH; f
1
= 1807.5 MHz; f
2
= 1877.5 MHz; RF performance at
V
DS
= 32 V; I
Dq
= 850 mA (main); V
GS(amp)peak
= 0.9 V; T
case
= 25
C; unless otherwise specified; in
an asymmetrical Doherty production test circuit at frequencies from 1805 MHz to 1880 MHz.
Symbol
G
p
RL
in
D
ACPR
Parameter
power gain
input return loss
drain efficiency
adjacent channel power ratio
Conditions
P
L(AV)
= 87 W
P
L(AV)
= 87 W
P
L(AV)
= 87 W
P
L(AV)
= 87 W
Min
15.2
-
41.5
-
Typ
16.2
15
45
39
Max
-
10
-
34
Unit
dB
dB
%
dBc
Table 8.
RF characteristics
Test signal: 1-carrier W-CDMA; PAR = 9.6 dB at 0.01 % probability on the CCDF;
3GPP test model 1; 1 to 64 DPCH; f = 1877.5 MHz; RF performance at V
DS
= 32 V;
I
Dq
= 850 mA (main); V
GS(amp)peak
= 0.9 V; T
case
= 25
C; unless otherwise specified; in an
asymmetrical Doherty production test circuit at a frequency of 1880 MHz.
Symbol
PAR
O
P
L(M)
Parameter
output peak-to-average ratio
peak output power
Conditions
P
L(AV)
= 120 W
P
L(AV)
= 120 W
Min
6.25
500
Typ
6.8
570
Max
-
-
Unit
dB
W
BLC9G20XS-400AVT
All information provided in this document is subject to legal disclaimers.
© Ampleon Netherlands B.V. 2017. All rights reserved.
Product data sheet
Rev. 3 — 24 November 2017
3 of 17
BLC9G20XS-400AVT
Power LDMOS transistor
7. Test information
7.1 Ruggedness in Doherty operation
The BLC9G20XS-400AVT is capable of withstanding a load mismatch corresponding to
VSWR = 10 : 1 through all phases under the following conditions: V
DS
= 32 V;
I
Dq
= 850 mA; V
GS(amp)peak
= 0.9 V; f = 1807.5 MHz; P
L
= 126 W (5 dB OBO); 100 %
clipping
.
7.2 Impedance information
Table 9.
Typical impedance of main device
Measured load-pull data of main device; I
Dq
= 800 mA (main); V
DS
= 32 V; pulsed CW (t
p
= 100
s;
= 10 %).
f
(MHz)
1805
1840
1880
1805
1840
1880
[1]
[2]
Z
S
[1]
()
1.0
j4.5
1.2
j4.8
1.3
j5.1
1.0
j4.5
1.1
j4.8
1.3
j5.1
Z
L
[1]
()
1.2
j3.0
1.2
j3.1
1.2
j3.1
2.5
j2.2
2.0
j2.5
2.0
j3.5
P
L
[2]
(W)
260
260
260
180
200
200
D
[2]
(%)
58.3
58.4
57.9
66.0
65.4
65.3
G
p
[2]
(dB)
19.2
19.4
19.3
21.7
21.3
21.3
Maximum power load
Maximum drain efficiency load
Z
S
and Z
L
defined in
Figure 1.
At 3 dB gain compression.
BLC9G20XS-400AVT
All information provided in this document is subject to legal disclaimers.
© Ampleon Netherlands B.V. 2017. All rights reserved.
Product data sheet
Rev. 3 — 24 November 2017
4 of 17
BLC9G20XS-400AVT
Power LDMOS transistor
Table 10. Typical impedance of peak device
Measured load-pull data of peak device; I
Dq
= 1800 mA (peak); V
DS
= 32 V; pulsed CW (t
p
= 100
s;
= 10 %).
f
(MHz)
1805
1840
1880
1805
1840
1880
[1]
[2]
Z
S
[1]
()
1.7
j6.0
2.3
j6.6
3.1
j7.1
1.7
j6.0
2.2
j6.6
3.1
j7.2
Z
L
[1]
()
1.7
j3.2
1.9
j3.3
1.9
j3.2
2.7
j2.9
2.6
j2.4
2.6
j2.3
P
L
[2]
(W)
430
430
430
380
360
360
D
[2]
(%)
56.4
56.4
56.4
63.8
63.5
63.7
G
p
[2]
(dB)
18.9
19.0
19.1
20.0
20.4
20.5
Maximum power load
Maximum drain efficiency load
Z
S
and Z
L
defined in
Figure 1.
At 3 dB gain compression.
drain
Z
L
gate
Z
S
001aaf059
Fig 1.
Definition of transistor impedance
7.3 Recommended impedances for Doherty design
Table 11. Typical impedance of main at 1 : 1 load
Measured load-pull data of main device; I
Dq
= 800 mA (main); V
DS
= 32 V; pulsed CW (t
p
= 100
s;
= 10 %).
f
(MHz)
1805
1840
1880
[1]
[2]
Z
S
[1]
()
1.0
j4.8
1.1
j5.0
1.1
j5.2
Z
L
[1]
()
1.4
j3.2
1.4
j2.9
1.4
j2.5
P
L(3dB)
[2]
(W)
210
210
205
D
[2]
(%)
42.0
42.3
44.0
G
p
[2]
(dB)
19.1
19.3
19.5
Z
S
and Z
L
defined in
Figure 1.
At P
L(AV)
= 85 W.
BLC9G20XS-400AVT
All information provided in this document is subject to legal disclaimers.
© Ampleon Netherlands B.V. 2017. All rights reserved.
Product data sheet
Rev. 3 — 24 November 2017
5 of 17
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