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74AC273SJ

Description
IC FF D-TYPE SNGL 8BIT 20SOP
Categorysemiconductor    logic   
File Size371KB,12 Pages
ManufacturerON Semiconductor
Websitehttp://www.onsemi.cn
Environmental Compliance
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74AC273SJ Overview

IC FF D-TYPE SNGL 8BIT 20SOP

74AC273SJ Parametric

Parameter NameAttribute value
Functionmaster reset
typeD type
Output typenon-inverting
Number of components1
bits per component8
Clock frequency175MHz
Maximum propagation delay at different V, maximum CL10ns @ 5V,50pF
Trigger typepositive edge
Current - output high, low24mA,24mA
Voltage - Power2 V ~ 6 V
Current - static (Iq)40µA
Input capacitance4.5pF
Operating temperature-40°C ~ 85°C(TA)
Installation typesurface mount
Package/casing20-SOIC (0.209", 5.30mm wide)
74AC273, 74ACT273 — Octal D-Type Flip-Flop
January 2008
74AC273, 74ACT273
Octal D-Type Flip-Flop
Features
Ideal buffer for microprocessor or memory
Eight edge-triggered D-type flip-flops
Buffered common clock
Buffered, asynchronous master reset
See 377 for clock enable version
See 373 for transparent latch version
See 374 for 3-STATE version
Outputs source/sink 24mA
74ACT273 has TTL-compatible inputs
General Description
The AC273 and ACT273 have eight edge-triggered
D-type flip-flops with individual D-type inputs and Q
outputs. The common buffered Clock (CP) and Master
Reset (MR) input load and reset (clear) all flip-flops
simultaneously.
The register is fully edge-triggered. The state of each
D-type input, one setup time before the LOW-to-HIGH
clock transition, is transferred to the corresponding flip-
flop's Q output.
All outputs will be forced LOW independently of Clock or
Data inputs by a LOW voltage level on the MR input. The
device is useful for applications where the true output
only is required and the Clock and Master Reset are
common to all storage elements.
Ordering Information
Order Number
74AC273SC
74AC273SJ
74AC273MTC
74AC273PC
74ACT273SC
74ACT273SJ
74ACT273MTC
Package
Number
M20B
M20D
MTC20
N20A
M20B
M20D
MTC20
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
©1988 Fairchild Semiconductor Corporation
74AC273, 74ACT273 Rev. 1.6.0
www.fairchildsemi.com
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