74LVT16240 • 74LVTH16240 Low Voltage 16-Bit Inverting Buffer/Line Driver with 3-STATE Outputs
March 1999
Revised June 2005
74LVT16240 • 74LVTH16240
Low Voltage 16-Bit Inverting Buffer/Line Driver
with 3-STATE Outputs
General Description
The LVT16240 and LVTH16240 contain sixteen inverting
buffers with 3-STATE outputs designed to be employed as
a memory and address driver, clock driver, or bus-oriented
transmitter/receiver. The device is nibble controlled.
Individual 3-STATE control inputs can be shorted together
for 8-bit or 16-bit operation.
The LVTH16240 data inputs include bushold, eliminating
the need for external pull-up resistors to hold unused
inputs.
These buffers and line drivers are designed for low-voltage
(3.3V) V
CC
applications, but with the capability to provide a
TTL interface to a 5V environment. The LVT16240 and
LVTH16240 are fabricated with an advanced BiCMOS
technology to achieve high speed operation similar to 5V
ABT while maintaining a low power dissipation.
Features
s
Input and output interface capability to systems at
5V V
CC
s
Bushold data inputs eliminate the need for external
pull-up resistors to hold unused inputs (74LVTH16240),
also available without bushold feature (74LVT16240)
s
Live insertion/extraction permitted
s
Power Up/Down high impedance provides glitch-free
bus loading
s
Outputs source/sink
32 mA/
64 mA
s
Functionally compatible with the 74 series 16240
s
Latch-up performance exceeds 500 mA
s
ESD performance:
Human-body model
!
2000V
Machine model
!
200V
Charged-device model
!
1000V
Ordering Code:
Order Number
74LVT16240MEA
74LVT16240MTD
74LVTH16240MEA
74LVTH16240MTD
Package
Number
MS48A
MTD48
MS48A
MTD48
Package Description
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
© 2005 Fairchild Semiconductor Corporation
DS012025
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74LVT16240 • 74LVTH16240
Connection Diagram
Pin Descriptions
Pin Names
OE
n
I
0
–I
15
O
0
–O
15
Description
Output Enable Inputs (Active LOW)
Inputs
3-STATE Outputs
Truth Table
Inputs
OE
1
L
L
H
Inputs
OE
2
L
L
H
X
Inputs
OE
3
L
L
H
Inputs
OE
4
L
L
H
H HIGH Voltage Level
L LOW Voltage Level
X Immaterial
Z High Impedance
Outputs
I
0
–I
3
L
H
X
O
0
–O
3
H
L
Z
Outputs
I
4
–I
7
L
H
O
4
–O
7
H
L
Z
Outputs
I
8
–I
11
L
H
X
O
8
–O
11
H
L
Z
Outputs
I
12
–I
15
L
H
X
O
12
–O
15
H
L
Z
Functional Description
The LVT16240 and LVTH16240 contain sixteen inverting buffers with 3-STATE standard outputs. The device is nibble
(4-bits) controlled with each nibble functioning identically, but independent of the other. The control pins may be shorted
together to obtain full 16-bit operation. The 3-STATE outputs are controlled by an Output Enable (OE
n
) input for each nib-
ble. When OE
n
is LOW, the outputs are in 2-state mode. When OE
n
is HIGH, the outputs are in the high impedance mode,
but this does not interfere with entering new data into the inputs.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
74LVT16240 • 74LVTH16240
Absolute Maximum Ratings
(Note 1)
Symbol
V
CC
V
I
V
O
I
IK
I
OK
I
O
I
CC
I
GND
T
STG
Parameter
Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Diode Current
DC Output Diode Current
DC Output Current
DC Supply Current per Supply Pin
DC Ground Current per Ground Pin
Storage Temperature
Value
Conditions
Units
V
V
Output in 3-STATE
Output in HIGH or LOW State (Note 2)
V
I
GND
V
O
GND
V
O
!
V
CC
Output at HIGH State
V
O
!
V
CC
Output at LOW State
mA
mA
mA
mA
mA
V
0.5 to
4.6
0.5 to
7.0
0.5 to
7.0
0.5 to V
CC
0.5
50
50
64
128
r
64
r
128
65 to
150
q
C
Recommended Operating Conditions
Symbol
V
CC
V
I
I
OH
I
OL
T
A
Supply Voltage
Input Voltage
HIGH Level Output Current
LOW Level Output Current
Free-Air Operating Temperature
Input Edge Rate, V
IN
0.8V–2.0V, V
CC
3.0V
Parameter
Min
2.7
0
Max
3.6
5.5
Units
V
V
mA
mA
32
64
40
0
85
10
q
C
ns/V
'
t/
'
V
Note 1:
Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions
beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied.
Note 2:
I
O
Absolute Maximum Rating must be observed.
DC Electrical Characteristics
Symbol
Parameter
V
CC
(V)
2.7
2.7–3.6
2.7–3.6
2.7–3.6
2.7
3.0
V
OL
Output LOW Voltage
2.7
2.7
3.0
3.0
3.0
I
I(HOLD)
(Note 4)
I
I(OD)
(Note 4)
I
I
Bushold Input Over-Drive
Current to Change State
Input Current
Control Pins
Data Pins
I
OFF
I
PU/PD
I
OZL
I
OZH
Power Off Leakage Current
Power Up/Down 3-STATE
Output Current
3-STATE Output Leakage Current
3-STATE Output Leakage Current
3.6
3.6
3.6
0
0–1.5V
3.6
3.6
3.0
Bushold Input Minimum Drive
3.0
75
V
CC
0.2
2.4
2.0
0.2
0.5
0.4
0.5
0.55
V
V
2.0
0.8
T
A
40
q
C to
85
q
C
Min
Typ
(Note 10)
V
IK
V
IH
V
IL
V
OH
Input Clamp Diode Voltage
Input HIGH Voltage
Input LOW Voltage
Output HIGH Voltage
Max
Units
Conditions
1.2
V
V
V
I
I
18 mA
V
O
d
0.1V or
V
O
t
V
CC
0.1V
I
OH
I
OH
I
OH
I
OL
I
OL
I
OL
I
OL
I
OL
V
I
V
I
100
P
A
8 mA
32 mA
100
P
A
24 mA
16 mA
32 mA
64 mA
0.8V
2.0V
75
500
P
A
P
A
10
(Note 5)
(Note 6)
V
I
5.5V
0V or V
CC
0V
V
CC
0.5V to 3.0V
GND or V
CC
0.5V
3.0V
V
I
V
I
V
I
500
r
1
5
1
P
A
r
100
r
100
5
5
P
A
P
A
P
A
P
A
0V
d
V
I
or V
O
d
5.5V
V
O
V
I
V
O
V
O
3
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74LVT16240 • 74LVTH16240
DC Electrical Characteristics
Symbol
I
OZH
I
CCH
I
CCL
I
CCZ
I
CCZH
Parameter
3-STATE Output Leakage Current
Power Supply Current
Power Supply Current
Power Supply Current
Power Supply Current
(Continued)
T
A
40
q
C to
85
q
C
Min
Typ
(Note 10)
3.6
3.6
3.6
3.6
3.6
10
0.19
5
0.19
0.19
Max
Units
Conditions
V
CC
V
O
d
5.5V
V
I
V
I
V
I
GND or V
CC
,
GND or V
CC
,
GND or V
CC
,
Outputs HIGH
mA
mA
mA
Outputs LOW
Outputs Disabled
V
I
GND or V
CC
,
V
CC
d
V
O
d
5.5V,
Outputs Disabled
One Input at V
CC
0.6V
Other Inputs at V
CC
or GND
V
CC
(V)
P
A
mA
'
I
CC
Increase in Power Supply Current
(Note 7)
3.3V, T
A
25
q
C.
3.6
0.2
mA
Note 3:
All typical values are at V
CC
Note 4:
Applies to bushold versions only (LVTH16240).
Note 5:
An external driver must source at least the specified current to switch from LOW-to-HIGH.
Note 6:
An external driver must sink at least the specified current to switch from HIGH-to-LOW.
Note 7:
This is the increase in supply current for each input that is at the specified voltage level rather than V
CC
or GND.
Dynamic Switching Characteristics
Symbol
V
OLP
V
OLV
Parameter
Quiet Output Maximum Dynamic V
OL
Quiet Output Minimum Dynamic V
OL
V
CC
(V)
3.3
3.3
(Note 8)
T
A
Min
25
q
C
Typ
0.8
Max
Units
V
V
Conditions
C
L
50 pF, R
L
(Note 9)
(Note 9)
500
:
0.8
Note 8:
Characterized in SSOP package. Guaranteed parameter, but not tested.
Note 9:
Max number of outputs defined as (n). n
1 data inputs are driven 0V to 3V. Output at LOW.
AC Electrical Characteristics
T
A
Symbol
Parameter
Min
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
OSHL
t
OSLH
Output to Output Skew
(Note 11)
3.3V, T
A
25
q
C.
40
q
C to
85
q
C, C
L
3.3V
r
0.3V
Typ
(Note 10)
50 pF, R
L
500
:
V
CC
2.7V
Max
4.2
4.0
4.9
6.1
5.2
4.4
1.0
Units
V
CC
Max
3.5
3.5
4.0
4.8
4.7
4.2
1.0
Min
1.0
1.0
1.0
1.2
1.7
1.7
Propagation Delay Data to Output
Output Enable Time
Output Disable Time
1.0
1.0
1.0
1.2
1.7
1.7
ns
ns
ns
ns
Note 10:
All typical values are at V
CC
Note 11:
Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t
OSHL
) or LOW-to-HIGH (t
OSLH
).
Capacitance
(Note 12)
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
Output Capacitance
V
CC
V
CC
0V, V
I
3.0V, V
O
Conditions
0V or V
CC
0V or V
CC
Typical
4
8
Units
pF
pF
Note 12:
Capacitance is measured at frequency f
1 MHz, per MIL-STD-883, Method 3012.
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74LVT16240 • 74LVTH16240
Physical Dimensions
inches (millimeters) unless otherwise noted
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
Package Number MS48A
5
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